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FMC ADC 100M 14b 4cha - Gateware
Commit d63286ab authored by mcattin's avatar mcattin
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Update DDR core. 

New generated core naming.


git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@125 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
parent e46239ae
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Showing with 1154 additions and 1050 deletions
hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
View file @ d63286ab
......@@ -1114,7 +1114,7 @@ begin
------------------------------------------------------------------------------
cmp_ddr_ctrl : ddr3_ctrl
generic map(
g_BANK_PORT_SELECT => "BANK3_64B_32B",
g_BANK_PORT_SELECT => "SPEC_BANK3_64B_32B",
g_MEMCLK_PERIOD => 3000,
g_SIMULATION => g_SIMULATION,
g_CALIB_SOFT_IP => g_CALIB_SOFT_IP,
......
hdl/spec/spec_top_fmc_adc_100Ms.ucf
View file @ d63286ab
......@@ -583,7 +583,7 @@ TIMESPEC TS_clk20_vcxo_i = PERIOD "clk20_vcxo_i_grp" 50 ns HIGH 50%;
# DDR3
NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/sys_clk_ibufg" TNM_NET = "SYS_CLK5";
NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/sys_clk_ibufg" TNM_NET = "SYS_CLK5";
TIMESPEC "TS_SYS_CLK5" = PERIOD "SYS_CLK5" 3.0 ns HIGH 50 %;
# ADC
......@@ -601,7 +601,7 @@ NET "cmp_gn4124_core/rst_*" TIG;
# DDR3
NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/c3_pll_lock" TIG;
NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/hard_done_cal" TIG;
NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL" TIG;
NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/c3_pll_lock" TIG;
NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/hard_done_cal" TIG;
NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL" TIG;
hdl/spec/syn/spec_fmc_adc_100Ms.xise
View file @ d63286ab
......@@ -958,177 +958,225 @@
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/rtl/ddr3_ctrl_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="176"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr3_ctrl_bank3_32b_32b/user_design/rtl/ddr3_ctrl_bank3_32b_32b.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/rtl/ddr3_ctrl_spec_bank3_32b_32b.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="177"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr3_ctrl_bank3_32b_32b/user_design/rtl/iodrp_controller.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/rtl/iodrp_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="178"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr3_ctrl_bank3_32b_32b/user_design/rtl/iodrp_mcb_controller.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/rtl/iodrp_mcb_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="179"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr3_ctrl_bank3_32b_32b/user_design/rtl/mcb_raw_wrapper.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/rtl/mcb_raw_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="180"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr3_ctrl_bank3_32b_32b/user_design/rtl/mcb_soft_calibration_top.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/rtl/mcb_soft_calibration_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="181"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr3_ctrl_bank3_32b_32b/user_design/rtl/mcb_soft_calibration.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/rtl/mcb_soft_calibration.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="182"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr3_ctrl_bank3_32b_32b/user_design/rtl/memc3_infrastructure.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/rtl/memc3_infrastructure.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="183"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr3_ctrl_bank3_32b_32b/user_design/rtl/memc3_wrapper.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/rtl/memc3_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="184"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr3_ctrl_bank3_64b_32b/user_design/rtl/ddr3_ctrl_bank3_64b_32b.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/ddr3_ctrl_spec_bank3_64b_32b.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="185"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr3_ctrl_bank3_64b_32b/user_design/rtl/iodrp_controller.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/iodrp_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="186"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr3_ctrl_bank3_64b_32b/user_design/rtl/iodrp_mcb_controller.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/iodrp_mcb_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="187"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr3_ctrl_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="188"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr3_ctrl_bank3_64b_32b/user_design/rtl/mcb_soft_calibration_top.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_soft_calibration_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="189"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr3_ctrl_bank3_64b_32b/user_design/rtl/mcb_soft_calibration.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_soft_calibration.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="190"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr3_ctrl_bank3_64b_32b/user_design/rtl/memc3_infrastructure.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_infrastructure.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="191"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr3_ctrl_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="192"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_bank4_32b_32b/user_design/rtl/ddr3_ctrl_bank4_32b_32b.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank4_32b_32b/user_design/rtl/ddr3_ctrl_svec_bank4_32b_32b.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="193"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_bank4_32b_32b/user_design/rtl/iodrp_controller.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank4_32b_32b/user_design/rtl/iodrp_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="194"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_bank4_32b_32b/user_design/rtl/iodrp_mcb_controller.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank4_32b_32b/user_design/rtl/iodrp_mcb_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="195"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_bank4_32b_32b/user_design/rtl/mcb_raw_wrapper.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank4_32b_32b/user_design/rtl/mcb_raw_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="196"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_bank4_32b_32b/user_design/rtl/mcb_soft_calibration_top.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank4_32b_32b/user_design/rtl/mcb_soft_calibration_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="197"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_bank4_32b_32b/user_design/rtl/mcb_soft_calibration.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank4_32b_32b/user_design/rtl/mcb_soft_calibration.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="198"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_bank4_32b_32b/user_design/rtl/memc4_infrastructure.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank4_32b_32b/user_design/rtl/memc4_infrastructure.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="199"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_bank4_32b_32b/user_design/rtl/memc4_wrapper.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank4_32b_32b/user_design/rtl/memc4_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="200"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_bank4_64b_32b/user_design/rtl/ddr3_ctrl_bank4_64b_32b.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank4_64b_32b/user_design/rtl/ddr3_ctrl_svec_bank4_64b_32b.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="201"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_bank4_64b_32b/user_design/rtl/iodrp_controller.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank4_64b_32b/user_design/rtl/iodrp_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="202"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_bank4_64b_32b/user_design/rtl/iodrp_mcb_controller.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank4_64b_32b/user_design/rtl/iodrp_mcb_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="203"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_bank4_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank4_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="204"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_bank4_64b_32b/user_design/rtl/mcb_soft_calibration_top.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank4_64b_32b/user_design/rtl/mcb_soft_calibration_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="205"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_bank4_64b_32b/user_design/rtl/mcb_soft_calibration.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank4_64b_32b/user_design/rtl/mcb_soft_calibration.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="206"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_bank4_64b_32b/user_design/rtl/memc4_infrastructure.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank4_64b_32b/user_design/rtl/memc4_infrastructure.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="207"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_bank4_64b_32b/user_design/rtl/memc4_wrapper.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank4_64b_32b/user_design/rtl/memc4_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="208"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_bank5_32b_32b/user_design/rtl/ddr3_ctrl_bank5_32b_32b.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_32b_32b/user_design/rtl/ddr3_ctrl_svec_bank5_32b_32b.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="209"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_bank5_32b_32b/user_design/rtl/iodrp_controller.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_32b_32b/user_design/rtl/iodrp_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="210"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_bank5_32b_32b/user_design/rtl/iodrp_mcb_controller.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_32b_32b/user_design/rtl/iodrp_mcb_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="211"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_bank5_32b_32b/user_design/rtl/mcb_raw_wrapper.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_32b_32b/user_design/rtl/mcb_raw_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="212"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_bank5_32b_32b/user_design/rtl/mcb_soft_calibration_top.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_32b_32b/user_design/rtl/mcb_soft_calibration_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="213"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_bank5_32b_32b/user_design/rtl/mcb_soft_calibration.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_32b_32b/user_design/rtl/mcb_soft_calibration.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="214"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_bank5_32b_32b/user_design/rtl/memc5_infrastructure.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_32b_32b/user_design/rtl/memc5_infrastructure.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="215"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_bank5_32b_32b/user_design/rtl/memc5_wrapper.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_32b_32b/user_design/rtl/memc5_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="216"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_bank5_64b_32b/user_design/rtl/ddr3_ctrl_bank5_64b_32b.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_64b_32b/user_design/rtl/ddr3_ctrl_svec_bank5_64b_32b.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="217"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_bank5_64b_32b/user_design/rtl/iodrp_controller.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_64b_32b/user_design/rtl/iodrp_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="218"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_bank5_64b_32b/user_design/rtl/iodrp_mcb_controller.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_64b_32b/user_design/rtl/iodrp_mcb_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="219"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_bank5_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="220"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_bank5_64b_32b/user_design/rtl/mcb_soft_calibration_top.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_64b_32b/user_design/rtl/mcb_soft_calibration_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="221"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_bank5_64b_32b/user_design/rtl/mcb_soft_calibration.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_64b_32b/user_design/rtl/mcb_soft_calibration.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="222"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_bank5_64b_32b/user_design/rtl/memc5_infrastructure.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_64b_32b/user_design/rtl/memc5_infrastructure.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="223"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_bank5_64b_32b/user_design/rtl/memc5_wrapper.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_64b_32b/user_design/rtl/memc5_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="224"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/vfc/ip_cores/ddr3_ctrl_vfc_bank1_32b_32b/user_design/rtl/ddr3_ctrl_vfc_bank1_32b_32b.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="225"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/vfc/ip_cores/ddr3_ctrl_vfc_bank1_32b_32b/user_design/rtl/iodrp_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="226"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/vfc/ip_cores/ddr3_ctrl_vfc_bank1_32b_32b/user_design/rtl/iodrp_mcb_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="227"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/p2l_des.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/vfc/ip_cores/ddr3_ctrl_vfc_bank1_32b_32b/user_design/rtl/mcb_raw_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="228"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/vfc/ip_cores/ddr3_ctrl_vfc_bank1_32b_32b/user_design/rtl/mcb_soft_calibration_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="229"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/vfc/ip_cores/ddr3_ctrl_vfc_bank1_32b_32b/user_design/rtl/mcb_soft_calibration.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="230"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/vfc/ip_cores/ddr3_ctrl_vfc_bank1_32b_32b/user_design/rtl/memc1_infrastructure.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="231"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/vfc/ip_cores/ddr3_ctrl_vfc_bank1_32b_32b/user_design/rtl/memc1_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="232"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/pulse_sync_rtl.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/vfc/ip_cores/ddr3_ctrl_vfc_bank1_64b_32b/user_design/rtl/ddr3_ctrl_vfc_bank1_64b_32b.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="233"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/vfc/ip_cores/ddr3_ctrl_vfc_bank1_64b_32b/user_design/rtl/iodrp_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="234"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/vfc/ip_cores/ddr3_ctrl_vfc_bank1_64b_32b/user_design/rtl/iodrp_mcb_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="235"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/vfc/ip_cores/ddr3_ctrl_vfc_bank1_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="236"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/vfc/ip_cores/ddr3_ctrl_vfc_bank1_64b_32b/user_design/rtl/mcb_soft_calibration_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="237"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/vfc/ip_cores/ddr3_ctrl_vfc_bank1_64b_32b/user_design/rtl/mcb_soft_calibration.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="238"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/vfc/ip_cores/ddr3_ctrl_vfc_bank1_64b_32b/user_design/rtl/memc1_infrastructure.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="239"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/vfc/ip_cores/ddr3_ctrl_vfc_bank1_64b_32b/user_design/rtl/memc1_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="240"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="241"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="242"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="243"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/p2l_des.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="244"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="245"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="246"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="247"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="248"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/pulse_sync_rtl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="249"/>
</file>
</files>
<bindings/>
......
hdl/spec/syn/spec_top_fmc_adc_100Ms.par
View file @ d63286ab
Release 13.3 par O.76xd (lin)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
pcbe15575:: Tue Jul 10 18:04:48 2012
pcbe15575:: Wed Jul 11 17:07:36 2012
par -w -intstyle ise -ol high -mt off spec_top_fmc_adc_100Ms_map.ncd
spec_top_fmc_adc_100Ms.ncd spec_top_fmc_adc_100Ms.pcf
......@@ -126,25 +126,25 @@ Phase 1 : 43543 unrouted; REAL time: 16 secs
Phase 2 : 33372 unrouted; REAL time: 20 secs
Phase 3 : 12946 unrouted; REAL time: 47 secs
Phase 3 : 12946 unrouted; REAL time: 48 secs
Phase 4 : 13097 unrouted; (Setup:0, Hold:357, Component Switching Limit:0) REAL time: 57 secs
Phase 4 : 13097 unrouted; (Setup:0, Hold:357, Component Switching Limit:0) REAL time: 58 secs
Updating file: spec_top_fmc_adc_100Ms.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:0, Hold:253, Component Switching Limit:0) REAL time: 1 mins 49 secs
Phase 5 : 0 unrouted; (Setup:0, Hold:253, Component Switching Limit:0) REAL time: 1 mins 51 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:253, Component Switching Limit:0) REAL time: 1 mins 49 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:253, Component Switching Limit:0) REAL time: 1 mins 51 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:253, Component Switching Limit:0) REAL time: 1 mins 49 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:253, Component Switching Limit:0) REAL time: 1 mins 51 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:253, Component Switching Limit:0) REAL time: 1 mins 49 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:253, Component Switching Limit:0) REAL time: 1 mins 51 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 49 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 51 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 52 secs
Total REAL time to Router completion: 1 mins 52 secs
Total CPU time to Router completion: 1 mins 55 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 54 secs
Total REAL time to Router completion: 1 mins 54 secs
Total CPU time to Router completion: 1 mins 57 secs
Partition Implementation Status
-------------------------------
......@@ -171,10 +171,10 @@ Generating Clock Report
| re/fs_clk | BUFGMUX_X2Y4| No | 155 | 0.257 | 1.473 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_ddr_ctrl/cmp_ddr | | | | | |
|3_ctrl_wrapper/gen_b | | | | | |
|ank3_64b_32b.cmp_ddr | | | | | |
|3_ctrl/c3_mcb_drp_cl | | | | | |
| k | BUFGMUX_X3Y13| No | 78 | 0.070 | 1.285 |
|3_ctrl_wrapper/gen_s | | | | | |
|pec_bank3_64b_32b.cm | | | | | |
|p_ddr3_ctrl/c3_mcb_d | | | | | |
| rp_clk | BUFGMUX_X3Y13| No | 78 | 0.070 | 1.285 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_gn4124_core/io_c | | | | | |
| lk | Local| | 41 | 0.064 | 1.562 |
......@@ -184,55 +184,56 @@ Generating Clock Report
| k_in_int_buf | Local| | 18 | 0.000 | 1.473 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_ddr_ctrl/cmp_ddr | | | | | |
|3_ctrl_wrapper/gen_b | | | | | |
|ank3_64b_32b.cmp_ddr | | | | | |
| 3_ctrl/c3_sysclk_2x | Local| | 35 | 0.576 | 1.548 |
|3_ctrl_wrapper/gen_s | | | | | |
|pec_bank3_64b_32b.cm | | | | | |
|p_ddr3_ctrl/c3_syscl | | | | | |
| k_2x | Local| | 35 | 0.576 | 1.548 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_ddr_ctrl/cmp_ddr | | | | | |
|3_ctrl_wrapper/gen_b | | | | | |
|ank3_64b_32b.cmp_ddr | | | | | |
|3_ctrl/memc3_wrapper | | | | | |
|_inst/memc3_mcb_raw_ | | | | | |
|wrapper_inst/ioi_drp | | | | | |
| _clk | Local| | 22 | 0.000 | 0.002 |
|3_ctrl_wrapper/gen_s | | | | | |
|pec_bank3_64b_32b.cm | | | | | |
|p_ddr3_ctrl/memc3_wr | | | | | |
|apper_inst/memc3_mcb | | | | | |
|_raw_wrapper_inst/io | | | | | |
| i_drp_clk | Local| | 22 | 0.000 | 0.002 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_ddr_ctrl/cmp_ddr | | | | | |
|3_ctrl_wrapper/gen_b | | | | | |
|ank3_64b_32b.cmp_ddr | | | | | |
|3_ctrl/c3_sysclk_2x_ | | | | | |
| 180 | Local| | 37 | 0.590 | 1.562 |
|3_ctrl_wrapper/gen_s | | | | | |
|pec_bank3_64b_32b.cm | | | | | |
|p_ddr3_ctrl/c3_syscl | | | | | |
| k_2x_180 | Local| | 37 | 0.590 | 1.562 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_ddr_ctrl/cmp_ddr | | | | | |
|3_ctrl_wrapper/gen_b | | | | | |
|ank3_64b_32b.cmp_ddr | | | | | |
|3_ctrl/memc3_wrapper | | | | | |
|_inst/memc3_mcb_raw_ | | | | | |
|wrapper_inst/idelay_ | | | | | |
| dqs_ioi_m | Local| | 1 | 0.000 | 0.002 |
|3_ctrl_wrapper/gen_s | | | | | |
|pec_bank3_64b_32b.cm | | | | | |
|p_ddr3_ctrl/memc3_wr | | | | | |
|apper_inst/memc3_mcb | | | | | |
|_raw_wrapper_inst/id | | | | | |
| elay_dqs_ioi_m | Local| | 1 | 0.000 | 0.002 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_ddr_ctrl/cmp_ddr | | | | | |
|3_ctrl_wrapper/gen_b | | | | | |
|ank3_64b_32b.cmp_ddr | | | | | |
|3_ctrl/memc3_wrapper | | | | | |
|_inst/memc3_mcb_raw_ | | | | | |
|wrapper_inst/idelay_ | | | | | |
| udqs_ioi_m | Local| | 1 | 0.000 | 0.002 |
|3_ctrl_wrapper/gen_s | | | | | |
|pec_bank3_64b_32b.cm | | | | | |
|p_ddr3_ctrl/memc3_wr | | | | | |
|apper_inst/memc3_mcb | | | | | |
|_raw_wrapper_inst/id | | | | | |
| elay_udqs_ioi_m | Local| | 1 | 0.000 | 0.002 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_ddr_ctrl/cmp_ddr | | | | | |
|3_ctrl_wrapper/gen_b | | | | | |
|ank3_64b_32b.cmp_ddr | | | | | |
|3_ctrl/memc3_wrapper | | | | | |
|_inst/memc3_mcb_raw_ | | | | | |
|wrapper_inst/idelay_ | | | | | |
| dqs_ioi_s | Local| | 1 | 0.000 | 0.002 |
|3_ctrl_wrapper/gen_s | | | | | |
|pec_bank3_64b_32b.cm | | | | | |
|p_ddr3_ctrl/memc3_wr | | | | | |
|apper_inst/memc3_mcb | | | | | |
|_raw_wrapper_inst/id | | | | | |
| elay_dqs_ioi_s | Local| | 1 | 0.000 | 0.002 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_ddr_ctrl/cmp_ddr | | | | | |
|3_ctrl_wrapper/gen_b | | | | | |
|ank3_64b_32b.cmp_ddr | | | | | |
|3_ctrl/memc3_wrapper | | | | | |
|_inst/memc3_mcb_raw_ | | | | | |
|wrapper_inst/idelay_ | | | | | |
| udqs_ioi_s | Local| | 1 | 0.000 | 0.002 |
|3_ctrl_wrapper/gen_s | | | | | |
|pec_bank3_64b_32b.cm | | | | | |
|p_ddr3_ctrl/memc3_wr | | | | | |
|apper_inst/memc3_mcb | | | | | |
|_raw_wrapper_inst/id | | | | | |
| elay_udqs_ioi_s | Local| | 1 | 0.000 | 0.002 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
......@@ -255,38 +256,39 @@ Asterisk (*) preceding a constraint indicates it was not met.
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
TS_cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen | MINPERIOD | 0.001ns| 1.499ns| 0| 0
_bank3_64b_32b_cmp_ddr3_ctrl_memc3_infras | | | | |
tructure_inst_clk_2x_0_0 = PERIOD | | | | |
TIMEGRP "cmp_ddr_ctrl_cmp_ddr3_c | | | | |
trl_wrapper_gen_bank3_64b_32b_cmp_ddr3_ct | | | | |
rl_memc3_infrastructure_inst_clk_2x_0_0" | | | | |
TS_ddr_clk_buf / 2 HIGH 50% | | | | |
_spec_bank3_64b_32b_cmp_ddr3_ctrl_memc3_i | | | | |
nfrastructure_inst_clk_2x_0_0 = P | | | | |
ERIOD TIMEGRP "cmp_ddr_ctrl_cmp_d | | | | |
dr3_ctrl_wrapper_gen_spec_bank3_64b_32b_c | | | | |
mp_ddr3_ctrl_memc3_infrastructure_inst_cl | | | | |
k_2x_0_0" TS_ddr_clk_buf / 2 HIGH | | | | |
50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen | MINPERIOD | 0.001ns| 1.499ns| 0| 0
_bank3_64b_32b_cmp_ddr3_ctrl_memc3_infras | | | | |
tructure_inst_clk_2x_180_0 = PERI | | | | |
OD TIMEGRP "cmp_ddr_ctrl_cmp_ddr3 | | | | |
_ctrl_wrapper_gen_bank3_64b_32b_cmp_ddr3_ | | | | |
ctrl_memc3_infrastructure_inst_clk_2x_180 | | | | |
_0" TS_ddr_clk_buf / 2 PHASE 0.75 | | | | |
ns HIGH 50% | | | | |
_spec_bank3_64b_32b_cmp_ddr3_ctrl_memc3_i | | | | |
nfrastructure_inst_clk_2x_180_0 = | | | | |
PERIOD TIMEGRP "cmp_ddr_ctrl_cmp | | | | |
_ddr3_ctrl_wrapper_gen_spec_bank3_64b_32b | | | | |
_cmp_ddr3_ctrl_memc3_infrastructure_inst_ | | | | |
clk_2x_180_0" TS_ddr_clk_buf / 2 | | | | |
PHASE 0.75 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen | MINPERIOD | 0.001ns| 1.499ns| 0| 0
_bank3_64b_32b_cmp_ddr3_ctrl_memc3_infras | | | | |
tructure_inst_clk_2x_0 = PERIOD T | | | | |
IMEGRP "cmp_ddr_ctrl_cmp_ddr3_ctr | | | | |
l_wrapper_gen_bank3_64b_32b_cmp_ddr3_ctrl | | | | |
_memc3_infrastructure_inst_clk_2x_0" | | | | |
TS_SYS_CLK5 / 2 HIGH 50% | | | | |
_spec_bank3_64b_32b_cmp_ddr3_ctrl_memc3_i | | | | |
nfrastructure_inst_clk_2x_0 = PER | | | | |
IOD TIMEGRP "cmp_ddr_ctrl_cmp_ddr | | | | |
3_ctrl_wrapper_gen_spec_bank3_64b_32b_cmp | | | | |
_ddr3_ctrl_memc3_infrastructure_inst_clk_ | | | | |
2x_0" TS_SYS_CLK5 / 2 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen | MINPERIOD | 0.001ns| 1.499ns| 0| 0
_bank3_64b_32b_cmp_ddr3_ctrl_memc3_infras | | | | |
tructure_inst_clk_2x_180 = PERIOD | | | | |
TIMEGRP "cmp_ddr_ctrl_cmp_ddr3_c | | | | |
trl_wrapper_gen_bank3_64b_32b_cmp_ddr3_ct | | | | |
rl_memc3_infrastructure_inst_clk_2x_180" | | | | |
TS_SYS_CLK5 / 2 PHASE 0.75 ns HIG | | | | |
H 50% | | | | |
_spec_bank3_64b_32b_cmp_ddr3_ctrl_memc3_i | | | | |
nfrastructure_inst_clk_2x_180 = P | | | | |
ERIOD TIMEGRP "cmp_ddr_ctrl_cmp_d | | | | |
dr3_ctrl_wrapper_gen_spec_bank3_64b_32b_c | | | | |
mp_ddr3_ctrl_memc3_infrastructure_inst_cl | | | | |
k_2x_180" TS_SYS_CLK5 / 2 PHASE 0 | | | | |
.75 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_sys_clk_125_buf = PERIOD TIMEGRP "sys_ | SETUP | 0.026ns| 7.974ns| 0| 0
clk_125_buf" TS_clk20_vcxo_i / 6.25 | HOLD | 0.355ns| | 0| 0
......@@ -333,13 +335,13 @@ Asterisk (*) preceding a constraint indicates it was not met.
cxo_i_grp" 50 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen | SETUP | 3.931ns| 8.068ns| 0| 0
_bank3_64b_32b_cmp_ddr3_ctrl_memc3_infras | HOLD | 0.428ns| | 0| 0
tructure_inst_mcb_drp_clk_bufg_in_0 | | | | |
= PERIOD TIMEGRP "cmp_ddr_ctrl | | | | |
_cmp_ddr3_ctrl_wrapper_gen_bank3_64b_32b_ | | | | |
cmp_ddr3_ctrl_memc3_infrastructure_inst_m | | | | |
cb_drp_clk_bufg_in_0" TS_ddr_clk_ | | | | |
buf / 0.25 HIGH 50% | | | | |
_spec_bank3_64b_32b_cmp_ddr3_ctrl_memc3_i | HOLD | 0.428ns| | 0| 0
nfrastructure_inst_mcb_drp_clk_bufg_in_0 | | | | |
= PERIOD TIMEGRP "cmp_ddr | | | | |
_ctrl_cmp_ddr3_ctrl_wrapper_gen_spec_bank | | | | |
3_64b_32b_cmp_ddr3_ctrl_memc3_infrastruct | | | | |
ure_inst_mcb_drp_clk_bufg_in_0" T | | | | |
S_ddr_clk_buf / 0.25 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_p2l_clkn = PERIOD TIMEGRP "p2l_clkn_gr | MINPERIOD | 4.075ns| 0.925ns| 0| 0
p" 5 ns HIGH 50% | | | | |
......@@ -348,13 +350,13 @@ Asterisk (*) preceding a constraint indicates it was not met.
p" 5 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen | MINPERIOD | 10.270ns| 1.730ns| 0| 0
_bank3_64b_32b_cmp_ddr3_ctrl_memc3_infras | | | | |
tructure_inst_mcb_drp_clk_bufg_in | | | | |
= PERIOD TIMEGRP "cmp_ddr_ctrl_c | | | | |
mp_ddr3_ctrl_wrapper_gen_bank3_64b_32b_cm | | | | |
p_ddr3_ctrl_memc3_infrastructure_inst_mcb | | | | |
_drp_clk_bufg_in" TS_SYS_CLK5 / 0 | | | | |
.25 HIGH 50% | | | | |
_spec_bank3_64b_32b_cmp_ddr3_ctrl_memc3_i | | | | |
nfrastructure_inst_mcb_drp_clk_bufg_in | | | | |
= PERIOD TIMEGRP "cmp_ddr_c | | | | |
trl_cmp_ddr3_ctrl_wrapper_gen_spec_bank3_ | | | | |
64b_32b_cmp_ddr3_ctrl_memc3_infrastructur | | | | |
e_inst_mcb_drp_clk_bufg_in" TS_SY | | | | |
S_CLK5 / 0.25 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_fmc_adc_100Ms_core_serdes_clk = PE | N/A | N/A| N/A| N/A| N/A
RIOD TIMEGRP "cmp_fmc_adc_100Ms_c | | | | |
......@@ -419,18 +421,18 @@ Derived Constraints for TS_clk20_vcxo_i
| TS_sys_clk_125_buf | 8.000ns| 7.974ns| N/A| 0| 0| 388937| 0|
| TS_ddr_clk_buf | 3.000ns| 2.572ns| 2.998ns| 0| 0| 0| 10400|
| TS_cmp_ddr_ctrl_cmp_ddr3_ctrl| 12.000ns| 8.068ns| N/A| 0| 0| 10400| 0|
| _wrapper_gen_bank3_64b_32b_cm| | | | | | | |
| p_ddr3_ctrl_memc3_infrastruct| | | | | | | |
| ure_inst_mcb_drp_clk_bufg_in_| | | | | | | |
| 0 | | | | | | | |
| _wrapper_gen_spec_bank3_64b_3| | | | | | | |
| 2b_cmp_ddr3_ctrl_memc3_infras| | | | | | | |
| tructure_inst_mcb_drp_clk_buf| | | | | | | |
| g_in_0 | | | | | | | |
| TS_cmp_ddr_ctrl_cmp_ddr3_ctrl| 1.500ns| 1.499ns| N/A| 0| 0| 0| 0|
| _wrapper_gen_bank3_64b_32b_cm| | | | | | | |
| p_ddr3_ctrl_memc3_infrastruct| | | | | | | |
| ure_inst_clk_2x_180_0 | | | | | | | |
| _wrapper_gen_spec_bank3_64b_3| | | | | | | |
| 2b_cmp_ddr3_ctrl_memc3_infras| | | | | | | |
| tructure_inst_clk_2x_180_0 | | | | | | | |
| TS_cmp_ddr_ctrl_cmp_ddr3_ctrl| 1.500ns| 1.499ns| N/A| 0| 0| 0| 0|
| _wrapper_gen_bank3_64b_32b_cm| | | | | | | |
| p_ddr3_ctrl_memc3_infrastruct| | | | | | | |
| ure_inst_clk_2x_0_0 | | | | | | | |
| _wrapper_gen_spec_bank3_64b_3| | | | | | | |
| 2b_cmp_ddr3_ctrl_memc3_infras| | | | | | | |
| tructure_inst_clk_2x_0_0 | | | | | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
Derived Constraints for TS_SYS_CLK5
......@@ -441,17 +443,17 @@ Derived Constraints for TS_SYS_CLK5
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_SYS_CLK5 | 3.000ns| 2.572ns| 2.998ns| 0| 0| 0| 0|
| TS_cmp_ddr_ctrl_cmp_ddr3_ctrl_| 12.000ns| 1.730ns| N/A| 0| 0| 0| 0|
| wrapper_gen_bank3_64b_32b_cmp_| | | | | | | |
| ddr3_ctrl_memc3_infrastructure| | | | | | | |
| _inst_mcb_drp_clk_bufg_in | | | | | | | |
| wrapper_gen_spec_bank3_64b_32b| | | | | | | |
| _cmp_ddr3_ctrl_memc3_infrastru| | | | | | | |
| cture_inst_mcb_drp_clk_bufg_in| | | | | | | |
| TS_cmp_ddr_ctrl_cmp_ddr3_ctrl_| 1.500ns| 1.499ns| N/A| 0| 0| 0| 0|
| wrapper_gen_bank3_64b_32b_cmp_| | | | | | | |
| ddr3_ctrl_memc3_infrastructure| | | | | | | |
| _inst_clk_2x_180 | | | | | | | |
| wrapper_gen_spec_bank3_64b_32b| | | | | | | |
| _cmp_ddr3_ctrl_memc3_infrastru| | | | | | | |
| cture_inst_clk_2x_180 | | | | | | | |
| TS_cmp_ddr_ctrl_cmp_ddr3_ctrl_| 1.500ns| 1.499ns| N/A| 0| 0| 0| 0|
| wrapper_gen_bank3_64b_32b_cmp_| | | | | | | |
| ddr3_ctrl_memc3_infrastructure| | | | | | | |
| _inst_clk_2x_0 | | | | | | | |
| wrapper_gen_spec_bank3_64b_32b| | | | | | | |
| _cmp_ddr3_ctrl_memc3_infrastru| | | | | | | |
| cture_inst_clk_2x_0 | | | | | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
Derived Constraints for TS_adc_dco_n_i
......@@ -481,8 +483,8 @@ All signals are completely routed.
WARNING:Par:283 - There are 7 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 1 mins 56 secs
Total CPU time to PAR completion: 1 mins 59 secs
Total REAL time to PAR completion: 1 mins 57 secs
Total CPU time to PAR completion: 2 mins
Peak Memory Usage: 342 MB
......
hdl/spec/syn/spec_top_fmc_adc_100Ms.syr
View file @ d63286ab
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/spec/syn/spec_top_fmc_adc_100Ms.twr
View file @ d63286ab
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/spec/syn/spec_top_fmc_adc_100Ms_map.mrp
View file @ d63286ab
......@@ -11,7 +11,7 @@ Target Device : xc6slx45t
Target Package : fgg484
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Tue Jul 10 18:00:09 2012
Mapped Date : Wed Jul 11 17:02:59 2012
Design Summary
--------------
......@@ -103,7 +103,7 @@ Specific Feature Utilization:
Average Fanout of Non-Clock Nets: 3.76
Peak Memory Usage: 411 MB
Total REAL time to MAP completion: 4 mins 33 secs
Total REAL time to MAP completion: 4 mins 32 secs
Total CPU time to MAP completion (all processors): 4 mins 36 secs
Table of Contents
......@@ -134,21 +134,21 @@ WARNING:MapLib:701 - Signal L_CLKn connected to top level port L_CLKn has been
WARNING:MapLib:701 - Signal DDR3_ZIO connected to top level port DDR3_ZIO has
been removed.
WARNING:MapLib:41 - All members of TNM group
"cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen_bank3_64b_32b_cmp_ddr3_ctrl_memc3_inf
rastructure_inst_clk0_bufg_in" have been optimized out of the design.
"cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen_spec_bank3_64b_32b_cmp_ddr3_ctrl_memc
3_infrastructure_inst_clk0_bufg_in" have been optimized out of the design.
WARNING:MapLib:41 - All members of TNM group
"cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen_bank3_64b_32b_cmp_ddr3_ctrl_memc3_inf
rastructure_inst_clk0_bufg_in_0" have been optimized out of the design.
"cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen_spec_bank3_64b_32b_cmp_ddr3_ctrl_memc
3_infrastructure_inst_clk0_bufg_in_0" have been optimized out of the design.
WARNING:MapLib:50 - The period specification
"TS_cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen_bank3_64b_32b_cmp_ddr3_ctrl_memc3_
infrastructure_inst_clk0_bufg_in" has been discarded because the group
"cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen_bank3_64b_32b_cmp_ddr3_ctrl_memc3_inf
rastructure_inst_clk0_bufg_in" has been optimized away.
"TS_cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen_spec_bank3_64b_32b_cmp_ddr3_ctrl_m
emc3_infrastructure_inst_clk0_bufg_in" has been discarded because the group
"cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen_spec_bank3_64b_32b_cmp_ddr3_ctrl_memc
3_infrastructure_inst_clk0_bufg_in" has been optimized away.
WARNING:MapLib:50 - The period specification
"TS_cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen_bank3_64b_32b_cmp_ddr3_ctrl_memc3_
infrastructure_inst_clk0_bufg_in_0" has been discarded because the group
"cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen_bank3_64b_32b_cmp_ddr3_ctrl_memc3_inf
rastructure_inst_clk0_bufg_in_0" has been optimized away.
"TS_cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen_spec_bank3_64b_32b_cmp_ddr3_ctrl_m
emc3_infrastructure_inst_clk0_bufg_in_0" has been discarded because the group
"cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen_spec_bank3_64b_32b_cmp_ddr3_ctrl_memc
3_infrastructure_inst_clk0_bufg_in_0" has been optimized away.
WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs
(RAMB8BWER). 9K Block RAM initialization data, both user defined and
default, may be incorrect and should not be used. For more information,
......@@ -160,8 +160,8 @@ INFO:Map:284 - Map is running with the multi-threading option on. Map currently
supports the use of up to 2 processors. Based on the the user options and
machine load, Map will use 2 processors during this run.
INFO:LIT:243 - Logical network
cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infr
astructure_inst/rst0_sync_r<24> has no load.
cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3
_infrastructure_inst/rst0_sync_r<24> has no load.
INFO:LIT:395 - The above info message is repeated 9 more times for the following
(max. 5 shown):
N640,
......@@ -204,176 +204,177 @@ above the place where that logic is listed in the trimming report, then locate
the lines that are least indented (begin at the leftmost edge).
The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/rst0_sync_r<24>" is loadless and has been removed.
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r<24>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/rst0_sync_r_24" (FF) removed.
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r_24" (FF) removed.
The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/clk0_bufg" is loadless and has been removed.
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/clk0_bufg" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/U_BUFG_CLK0" (CKBUF) removed.
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/U_BUFG_CLK0" (CKBUF) removed.
The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/clk0_bufg_in" is loadless and has been removed.
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/clk0_bufg_in" is loadless and has been removed.
The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/rst0_sync_r<23>" is loadless and has been removed.
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r<23>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/rst0_sync_r_23" (FF) removed.
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r_23" (FF) removed.
The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/rst0_sync_r<22>" is loadless and has been removed.
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r<22>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/rst0_sync_r_22" (FF) removed.
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r_22" (FF) removed.
The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/rst0_sync_r<21>" is loadless and has been removed.
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r<21>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/rst0_sync_r_21" (FF) removed.
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r_21" (FF) removed.
The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/rst0_sync_r<20>" is loadless and has been removed.
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r<20>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/rst0_sync_r_20" (FF) removed.
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r_20" (FF) removed.
The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/rst0_sync_r<19>" is loadless and has been removed.
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r<19>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/rst0_sync_r_19" (FF) removed.
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r_19" (FF) removed.
The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/rst0_sync_r<18>" is loadless and has been removed.
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r<18>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/rst0_sync_r_18" (FF) removed.
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r_18" (FF) removed.
The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/rst0_sync_r<17>" is loadless and has been removed.
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r<17>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/rst0_sync_r_17" (FF) removed.
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r_17" (FF) removed.
The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/rst0_sync_r<16>" is loadless and has been removed.
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r<16>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/rst0_sync_r_16" (FF) removed.
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r_16" (FF) removed.
The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/rst0_sync_r<15>" is loadless and has been removed.
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r<15>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/rst0_sync_r_15" (FF) removed.
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r_15" (FF) removed.
The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/rst0_sync_r<14>" is loadless and has been removed.
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r<14>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/rst0_sync_r_14" (FF) removed.
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r_14" (FF) removed.
The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/rst0_sync_r<13>" is loadless and has been removed.
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r<13>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/rst0_sync_r_13" (FF) removed.
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r_13" (FF) removed.
The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/rst0_sync_r<12>" is loadless and has been removed.
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r<12>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/rst0_sync_r_12" (FF) removed.
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r_12" (FF) removed.
The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/rst0_sync_r<11>" is loadless and has been removed.
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r<11>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/rst0_sync_r_11" (FF) removed.
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r_11" (FF) removed.
The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/rst0_sync_r<10>" is loadless and has been removed.
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r<10>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/rst0_sync_r_10" (FF) removed.
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r_10" (FF) removed.
The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/rst0_sync_r<9>" is loadless and has been removed.
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r<9>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/rst0_sync_r_9" (FF) removed.
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r_9" (FF) removed.
The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/rst0_sync_r<8>" is loadless and has been removed.
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r<8>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/rst0_sync_r_8" (FF) removed.
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r_8" (FF) removed.
The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/rst0_sync_r<7>" is loadless and has been removed.
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r<7>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/rst0_sync_r_7" (FF) removed.
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r_7" (FF) removed.
The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/rst0_sync_r<6>" is loadless and has been removed.
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r<6>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/rst0_sync_r_6" (FF) removed.
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r_6" (FF) removed.
The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/rst0_sync_r<5>" is loadless and has been removed.
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r<5>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/rst0_sync_r_5" (FF) removed.
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r_5" (FF) removed.
The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/rst0_sync_r<4>" is loadless and has been removed.
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r<4>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/rst0_sync_r_4" (FF) removed.
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r_4" (FF) removed.
The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/rst0_sync_r<3>" is loadless and has been removed.
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r<3>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/rst0_sync_r_3" (FF) removed.
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r_3" (FF) removed.
The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/rst0_sync_r<2>" is loadless and has been removed.
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r<2>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/rst0_sync_r_2" (FF) removed.
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r_2" (FF) removed.
The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/rst0_sync_r<1>" is loadless and has been removed.
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r<1>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/rst0_sync_r_1" (FF) removed.
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r_1" (FF) removed.
The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/rst0_sync_r<0>" is loadless and has been removed.
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r<0>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/rst0_sync_r_0" (FF) removed.
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r_0" (FF) removed.
*The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/rst_tmp" is loadless and has been removed.
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst_tmp" is loadless and has been removed.
* Loadless block
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/rst_tmp1" (ROM) removed.
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst_tmp1" (ROM) removed.
* The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/syn_clk0_powerup_pll_locked" is loadless and has been removed.
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/syn_clk0_powerup_pll_locked" is loadless and has been
removed.
* Loadless block
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/syn_clk0_powerup_pll_locked" (FF) removed.
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/syn_clk0_powerup_pll_locked" (FF) removed.
Loadless block "cmp_clk_250_buf" (CKBUF) removed.
The signal "sys_clk_250_buf" is loadless and has been removed.
Loadless block
......
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