Update DDR core.

New generated core naming. git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@125 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4

Update DDR core.
New generated core naming. git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@125 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
d63286ab · mcattin · e46239ae · d63286ab · d63286ab · d63286ab
Commit d63286ab authored Jul 11, 2012 by mcattin
7 changed files
--- a/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
+++ b/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
@@ -1114,7 +1114,7 @@ begin
  ------------------------------------------------------------------------------
  cmp_ddr_ctrl : ddr3_ctrl
    generic map(
-      g_BANK_PORT_SELECT   => "BANK3_64B_32B",
+      g_BANK_PORT_SELECT   => "SPEC_BANK3_64B_32B",
      g_MEMCLK_PERIOD      => 3000,
      g_SIMULATION         => g_SIMULATION,
      g_CALIB_SOFT_IP      => g_CALIB_SOFT_IP,

--- a/hdl/spec/spec_top_fmc_adc_100Ms.ucf
+++ b/hdl/spec/spec_top_fmc_adc_100Ms.ucf
@@ -583,7 +583,7 @@ TIMESPEC TS_clk20_vcxo_i = PERIOD "clk20_vcxo_i_grp" 50 ns HIGH 50%;

 # DDR3

-NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/sys_clk_ibufg" TNM_NET = "SYS_CLK5";
+NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/sys_clk_ibufg" TNM_NET = "SYS_CLK5";
 TIMESPEC "TS_SYS_CLK5" = PERIOD "SYS_CLK5"  3.0  ns HIGH 50 %;

 # ADC
@@ -601,7 +601,7 @@ NET "cmp_gn4124_core/rst_*" TIG;

 # DDR3

-NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
-NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/c3_pll_lock" TIG;
-NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/hard_done_cal" TIG;
-NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL" TIG;
+NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
+NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/c3_pll_lock" TIG;
+NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/hard_done_cal" TIG;
+NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL" TIG;
--- a/hdl/spec/syn/spec_fmc_adc_100Ms.xise
+++ b/hdl/spec/syn/spec_fmc_adc_100Ms.xise
--- a/hdl/spec/syn/spec_top_fmc_adc_100Ms.par
+++ b/hdl/spec/syn/spec_top_fmc_adc_100Ms.par
--- a/hdl/spec/syn/spec_top_fmc_adc_100Ms.syr
+++ b/hdl/spec/syn/spec_top_fmc_adc_100Ms.syr
--- a/hdl/spec/syn/spec_top_fmc_adc_100Ms.twr
+++ b/hdl/spec/syn/spec_top_fmc_adc_100Ms.twr
--- a/hdl/spec/syn/spec_top_fmc_adc_100Ms_map.mrp
+++ b/hdl/spec/syn/spec_top_fmc_adc_100Ms_map.mrp