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FMC ADC 100M 14b 4cha - Gateware
Commit 94c7ce24 authored by Matthieu Cattin's avatar Matthieu Cattin
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doc: Re-organise the documentation folder. 

- Rename folders with shorter names.
- Remove documents un-related to gateware (e.g. board design).
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.gitignore
View file @ 94c7ce24
...@@ -65,7 +65,7 @@ hdl/svec/sim/testbench/transcript ...@@ -65,7 +65,7 @@ hdl/svec/sim/testbench/transcript
hdl/svec/sim/testbench/vsim.wlf hdl/svec/sim/testbench/vsim.wlf
hdl/svec/sim/testbench/vsim_stacktrace.vstf hdl/svec/sim/testbench/vsim_stacktrace.vstf
hdl/svec/sim/testbench/work/ hdl/svec/sim/testbench/work/
documentation/manuals/*/*.html doc/manual/*.html
*.texi *.texi
*.aux *.aux
*.log *.log
......
documentation/manuals/gateware/fmcadc100m14b4cha_gateware_manual.in → doc/manual/fmcadc100m14b4cha_gateware_manual.in
View file @ 94c7ce24
...@@ -44,7 +44,7 @@ ...@@ -44,7 +44,7 @@
@subtitle @value{update-month} - Release 4.0 @subtitle @value{update-month} - Release 4.0
@subtitle For PCIe (SPEC) and VME64x (SVEC) FMC Carriers @subtitle For PCIe (SPEC) and VME64x (SVEC) FMC Carriers
@sp 10 @sp 10
@center @image{../../figures/cern_logo,3cm,,,pdf} @hfill @image{../../figures/ohr_logo,3cm,,,pdf} @center @image{../fig/cern_logo,3cm,,,pdf} @hfill @image{../fig/ohr_logo,3cm,,,pdf}
@author Matthieu Cattin (CERN) @author Matthieu Cattin (CERN)
@end titlepage @end titlepage
@headings single @headings single
...@@ -212,7 +212,7 @@ The @ref{fig:spec_fw_arch} illustrates the fmc-adc gateware architecture on the ...@@ -212,7 +212,7 @@ The @ref{fig:spec_fw_arch} illustrates the fmc-adc gateware architecture on the
A crossbar from the general-cores@footnote{@uref{http://www.ohwr.org/projects/general-cores}} library is used to map the slaves in the Wishbone address space. A crossbar from the general-cores@footnote{@uref{http://www.ohwr.org/projects/general-cores}} library is used to map the slaves in the Wishbone address space.
@float Figure,fig:spec_fw_arch @float Figure,fig:spec_fw_arch
@center @image{../../figures/spec_fw_arch, 15cm,,,pdf} @center @image{../fig/spec_fw_arch, 15cm,,,pdf}
@caption{FMC-ADC gateware architecture on SPEC carrier.} @caption{FMC-ADC gateware architecture on SPEC carrier.}
@end float @end float
...@@ -362,7 +362,7 @@ In the VME64x version of the gateware, all blocks are connected to the VME64x co ...@@ -362,7 +362,7 @@ In the VME64x version of the gateware, all blocks are connected to the VME64x co
A crossbar from the general-cores@footnote{@uref{http://www.ohwr.org/projects/general-cores}} library is used to map the slaves in the Wishbone address space. A crossbar from the general-cores@footnote{@uref{http://www.ohwr.org/projects/general-cores}} library is used to map the slaves in the Wishbone address space.
@float Figure,fig:svec_fw_arch @float Figure,fig:svec_fw_arch
@center @image{../../figures/svec_fw_arch, 15cm,,,pdf} @center @image{../fig/svec_fw_arch, 15cm,,,pdf}
@caption{FMC-ADC gateware architecture on SVEC carrier.} @caption{FMC-ADC gateware architecture on SVEC carrier.}
@end float @end float
...@@ -760,7 +760,7 @@ The four channels data and the trigger signal are synchronised to the system clo ...@@ -760,7 +760,7 @@ The four channels data and the trigger signal are synchronised to the system clo
The configuration signals coming from registers in the system clock domain are synchronised to the sampling clock within the Wishbone slave (@command{wbgen2} feature). The configuration signals coming from registers in the system clock domain are synchronised to the sampling clock within the Wishbone slave (@command{wbgen2} feature).
@float Figure,fig:adc_core_fs_clk @float Figure,fig:adc_core_fs_clk
@center @image{../../figures/adc_core_fs_clk, 14cm,,,pdf} @center @image{../fig/adc_core_fs_clk, 14cm,,,pdf}
@caption{ADC core diagram (sampling clock domain).} @caption{ADC core diagram (sampling clock domain).}
@end float @end float
...@@ -769,7 +769,7 @@ In the fmc-adc application, the default configuration is kept. ...@@ -769,7 +769,7 @@ In the fmc-adc application, the default configuration is kept.
The figure @ref{fig:ltc2174_mode} is an extract from the LTC2174 datasheet illustrating the @i{2-Lane Output Mode, 16-Bit Serialization} waveforms. The figure @ref{fig:ltc2174_mode} is an extract from the LTC2174 datasheet illustrating the @i{2-Lane Output Mode, 16-Bit Serialization} waveforms.
@float Figure,fig:ltc2174_mode @float Figure,fig:ltc2174_mode
@center @image{../../figures/ltc2174_mode, 12cm,,,pdf} @center @image{../fig/ltc2174_mode, 12cm,,,pdf}
@caption{LTC2174 data output mode waveforms.} @caption{LTC2174 data output mode waveforms.}
@end float @end float
...@@ -805,7 +805,7 @@ In addition to the three ranges for normal operation, there are three more confi ...@@ -805,7 +805,7 @@ In addition to the three ranges for normal operation, there are three more confi
Opto-isolated analogue switches allow the different configurations. They are represented by normal switched in the simplified schematics. Opto-isolated analogue switches allow the different configurations. They are represented by normal switched in the simplified schematics.
@float Figure,fig:analogue_input @float Figure,fig:analogue_input
@center @image{../../figures/analogue_input, 10cm,,,pdf} @center @image{../fig/analogue_input, 10cm,,,pdf}
@caption{Simplified schematics of the analogue input.} @caption{Simplified schematics of the analogue input.}
@end float @end float
...@@ -872,7 +872,7 @@ The delay generator allows to insert an defined number of sampling clock period ...@@ -872,7 +872,7 @@ The delay generator allows to insert an defined number of sampling clock period
The @ref{fig:trig_unit} shows a simplified digram of trigger unit. The @ref{fig:trig_unit} shows a simplified digram of trigger unit.
@float Figure,fig:trig_unit @float Figure,fig:trig_unit
@center @image{../../figures/trigger_unit, 12cm,,,pdf} @center @image{../fig/trigger_unit, 12cm,,,pdf}
@caption{Trigger unit diagram.} @caption{Trigger unit diagram.}
@end float @end float
...@@ -907,7 +907,7 @@ The software trigger source consists in a pulse generated when a write cycle is ...@@ -907,7 +907,7 @@ The software trigger source consists in a pulse generated when a write cycle is
For further information on the trigger configuration registers @pxref{ADC Core Registers}. For further information on the trigger configuration registers @pxref{ADC Core Registers}.
@float Figure,fig:trig_hw_int @float Figure,fig:trig_hw_int
@center @image{../../figures/trig_hw_int, 8cm,,,pdf} @center @image{../fig/trig_hw_int, 8cm,,,pdf}
@caption{Internal hardware trigger threshold.} @caption{Internal hardware trigger threshold.}
@end float @end float
...@@ -971,7 +971,7 @@ Two registers per channel are implemented in the FPGA for ADC gain and offset co ...@@ -971,7 +971,7 @@ Two registers per channel are implemented in the FPGA for ADC gain and offset co
When an input range is selected, the corresponding gain/offset correction values must be loaded from the EEPROM to those registers. When an input range is selected, the corresponding gain/offset correction values must be loaded from the EEPROM to those registers.
@float Figure,fig:off_gain_corr @float Figure,fig:off_gain_corr
@center @image{../../figures/offset_gain_corr, 12cm,,,pdf} @center @image{../fig/offset_gain_corr, 12cm,,,pdf}
@caption{ADC offset and gain correction block.} @caption{ADC offset and gain correction block.}
@end float @end float
...@@ -980,7 +980,7 @@ The gain register takes a 16-bit fixed point value. ...@@ -980,7 +980,7 @@ The gain register takes a 16-bit fixed point value.
The fixed point format is as follow: The fixed point format is as follow:
@float Figure,fig:adc_gain_format @float Figure,fig:adc_gain_format
@center @image{../../figures/adc_gain_format, 13cm,,,pdf} @center @image{../fig/adc_gain_format, 13cm,,,pdf}
@caption{ADC gain register format.} @caption{ADC gain register format.}
@end float @end float
...@@ -1034,7 +1034,7 @@ Along the datapath, we call @i{sample} a 64-bit vector containing a sample for e ...@@ -1034,7 +1034,7 @@ Along the datapath, we call @i{sample} a 64-bit vector containing a sample for e
At the output of the ADC core, a flow control FIFO allows to cope with the memory controller temporary unavailabilities (due to DDR refresh cycles). At the output of the ADC core, a flow control FIFO allows to cope with the memory controller temporary unavailabilities (due to DDR refresh cycles).
@float Figure,fig:adc_core_sys_clk @float Figure,fig:adc_core_sys_clk
@center @image{../../figures/adc_core_sys_clk, 15cm,,,pdf} @center @image{../fig/adc_core_sys_clk, 15cm,,,pdf}
@caption{Acquisition logic diagram (system clock domain).} @caption{Acquisition logic diagram (system clock domain).}
@end float @end float
...@@ -1044,7 +1044,7 @@ The DDR memory size is 2Gb or 256MB. ...@@ -1044,7 +1044,7 @@ The DDR memory size is 2Gb or 256MB.
@w{It means that the maximum number of samples that can be stored is 128M samples (@math{2^{27}*16}).} @w{It means that the maximum number of samples that can be stored is 128M samples (@math{2^{27}*16}).}
@float Figure,fig:mem_samples @float Figure,fig:mem_samples
@center @image{../../figures/memory_samples, 15cm,,,pdf} @center @image{../fig/memory_samples, 15cm,,,pdf}
@caption{Illustration of samples storage in DDR memory.} @caption{Illustration of samples storage in DDR memory.}
@end float @end float
...@@ -1071,7 +1071,7 @@ An interrupt is generated when the acquisition ends. ...@@ -1071,7 +1071,7 @@ An interrupt is generated when the acquisition ends.
@b{Note:} After a stop command, no end of acquisition interrupt is generated. @b{Note:} After a stop command, no end of acquisition interrupt is generated.
@float Figure,fig:acq_fsm @float Figure,fig:acq_fsm
@center @image{../../figures/acq_fsm, 10cm,,,pdf} @center @image{../fig/acq_fsm, 10cm,,,pdf}
@caption{Acquisition state machine.} @caption{Acquisition state machine.}
@end float @end float
...@@ -1119,12 +1119,12 @@ The @ref{fig:mem_single_shot} and @ref{fig:mem_single_shot_overlap} illustrate t ...@@ -1119,12 +1119,12 @@ The @ref{fig:mem_single_shot} and @ref{fig:mem_single_shot_overlap} illustrate t
The acquisition state machine is also represented. The acquisition state machine is also represented.
@float Figure,fig:mem_single_shot @float Figure,fig:mem_single_shot
@center @image{../../figures/memory_single-shot, 15cm,,,pdf} @center @image{../fig/memory_single-shot, 15cm,,,pdf}
@caption{Single-shot mode acquisition example.} @caption{Single-shot mode acquisition example.}
@end float @end float
@float Figure,fig:mem_single_shot_overlap @float Figure,fig:mem_single_shot_overlap
@center @image{../../figures/memory_single-shot_overlap, 15cm,,,pdf} @center @image{../fig/memory_single-shot_overlap, 15cm,,,pdf}
@caption{Single-shot mode acquisition example (overlapping DDR memory).} @caption{Single-shot mode acquisition example (overlapping DDR memory).}
@end float @end float
...@@ -1157,7 +1157,7 @@ Then the second shot is written right after the trigger time-tag of the first sh ...@@ -1157,7 +1157,7 @@ Then the second shot is written right after the trigger time-tag of the first sh
The @ref{fig:mem_multi_shot} shows the shots organisation in the DDR memory. The @ref{fig:mem_multi_shot} shows the shots organisation in the DDR memory.
@float Figure,fig:mem_multi_shot @float Figure,fig:mem_multi_shot
@center @image{../../figures/memory_multi-shot, 15cm,,,pdf} @center @image{../fig/memory_multi-shot, 15cm,,,pdf}
@caption{DDR memory usage in multi-shot mode acquisition.} @caption{DDR memory usage in multi-shot mode acquisition.}
@end float @end float
......
hdl/adc/wb_gen/Makefile
View file @ 94c7ce24
WBGEN2=~/projects/wbgen2/wbgen2 WBGEN2=~/projects/wbgen2/wbgen2
RTL=../rtl/ RTL=../rtl/
TEX=../../../documentation/manuals/gateware/ TEX=../../../doc/manual/
fmc_adc_100Ms_csr: fmc_adc_100Ms_csr:
$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -f html -D $@.htm -C $@.h $@.wb $(WBGEN2) -l vhdl -V $(RTL)$@.vhd -f html -D $@.htm -C $@.h $@.wb
......
hdl/ip_cores/timetag_core/wb_gen/Makefile
View file @ 94c7ce24
WBGEN2=~/projects/wbgen2/wbgen2 WBGEN2=~/projects/wbgen2/wbgen2
RTL=../rtl/ RTL=../rtl/
TEX=../../../../documentation/manuals/firmware/ TEX=../../../../doc/manual/
timetag_core_regs: timetag_core_regs:
$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -f html -D $@.htm -C $@.h $@.wb $(WBGEN2) -l vhdl -V $(RTL)$@.vhd -f html -D $@.htm -C $@.h $@.wb
......
hdl/spec/wb_gen/Makefile
View file @ 94c7ce24
WBGEN2=~/projects/wbgen2/wbgen2 WBGEN2=~/projects/wbgen2/wbgen2
RTL=../rtl/ RTL=../rtl/
TEX=../../../documentation/manuals/gateware/spec/ TEX=../../../doc/manual/spec/
carrier_csr: carrier_csr:
$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -f html -D $@.htm -C $@.h $@.wb $(WBGEN2) -l vhdl -V $(RTL)$@.vhd -f html -D $@.htm -C $@.h $@.wb
......
hdl/svec/wb_gen/Makefile
View file @ 94c7ce24
WBGEN2=~/projects/wbgen2/wbgen2 WBGEN2=~/projects/wbgen2/wbgen2
RTL=../rtl/ RTL=../rtl/
TEX=../../../documentation/manuals/gateware/svec/ TEX=../../../doc/manual//svec/
carrier_csr: carrier_csr:
$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -f html -D $@.htm -C $@.h $@.wb $(WBGEN2) -l vhdl -V $(RTL)$@.vhd -f html -D $@.htm -C $@.h $@.wb
......
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