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FMC ADC 100M 14b 4cha - Gateware
Commit 8e4884b9 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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sim: updated SVEC sim to verify new timetag functionality

parent 77214b2e
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Showing with 90 additions and 70 deletions
hdl/svec/sim/testbench/main.sv
View file @ 8e4884b9
...@@ -130,9 +130,9 @@ module main; ...@@ -130,9 +130,9 @@ module main;
$display("Release FMC0/1 reset\n"); $display("Release FMC0/1 reset\n");
acc.write('h120C, 'h0, A32|SINGLE|D32); acc.write('h120C, 'h0, A32|SINGLE|D32);
// Trigger setup (sw trigger) // Trigger setup (time trigger)
$display("Trigger setup\n"); $display("Trigger setup\n");
acc.write('h3308, 'h8, A32|SINGLE|D32); acc.write('h3308, 'hA, A32|SINGLE|D32);
// Acquisition setup // Acquisition setup
$display("Acquisition setup\n"); $display("Acquisition setup\n");
...@@ -151,17 +151,28 @@ module main; ...@@ -151,17 +151,28 @@ module main;
acc.write('h3600, 'h00000032); // timetag core seconds high acc.write('h3600, 'h00000032); // timetag core seconds high
acc.write('h3604, 'h00005a34); // timetag core seconds low acc.write('h3604, 'h00005a34); // timetag core seconds low
acc.write('h3608, 'h00000000); // timetag core ticks acc.write('h3608, 'h07735930); // timetag core ticks
// Start acquisition // Start acquisition
$display("Start acquisition\n"); $display("Start acquisition\n");
acc.write('h3300, 'h1, A32|SINGLE|D32); // Send START command acc.write('h3300, 'h1, A32|SINGLE|D32); // Send START command
// Start acquisition
$display("Schedule time trigger\n");
acc.write('h360C, 'h00000032); // time trigger seconds high
acc.write('h3610, 'h00005a35); // time trigger seconds low
acc.write('h3614, 'h00000300); // time trigger core ticks
// Sw trigger // Sw trigger
/* -----\/----- EXCLUDED -----\/-----
#1us #1us
$display("Software trigger\n"); $display("Set trigger time\n");
acc.write('h3310, 'hFF, A32|SINGLE|D32); acc.write('h3310, 'hFF, A32|SINGLE|D32);
-----/\----- EXCLUDED -----/\----- */
#20us;
/* /*
// Data "FIFO" test // Data "FIFO" test
acc.write('h2200, 'h0, A32|SINGLE|D32); acc.write('h2200, 'h0, A32|SINGLE|D32);
......
hdl/svec/sim/testbench/svec.do
View file @ 8e4884b9
...@@ -10,7 +10,7 @@ set NumericStdNoWarnings 1 ...@@ -10,7 +10,7 @@ set NumericStdNoWarnings 1
do wave.do do wave.do
radix -hexadecimal radix -hexadecimal
run 50 us run 60 us
hdl/svec/sim/testbench/wave.do
View file @ 8e4884b9
...@@ -3,71 +3,80 @@ quietly WaveActivateNextPane {} 0 ...@@ -3,71 +3,80 @@ quietly WaveActivateNextPane {} 0
add wave -noupdate /main/DUT/sys_clk_62_5 add wave -noupdate /main/DUT/sys_clk_62_5
add wave -noupdate /main/DUT/sys_clk_125 add wave -noupdate /main/DUT/sys_clk_125
add wave -noupdate /main/DUT/powerup* add wave -noupdate /main/DUT/powerup*
add wave -noupdate -divider {wb vme} add wave -noupdate -group ADC_CORE0 /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sys_clk_i
add wave -noupdate /main/DUT/cnx_slave_in(0).cyc add wave -noupdate -group ADC_CORE0 /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sys_rst_n_i
add wave -noupdate /main/DUT/cnx_slave_in(0).stb add wave -noupdate -group ADC_CORE0 /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk
add wave -noupdate /main/DUT/cnx_slave_in(0).we add wave -noupdate -group ADC_CORE0 /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_rst_n
add wave -noupdate -radix hexadecimal /main/DUT/cnx_slave_in(0).adr add wave -noupdate -group ADC_CORE0 /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/acq_fsm_current_state
add wave -noupdate -radix hexadecimal /main/DUT/cnx_slave_in(0).dat add wave -noupdate -group ADC_CORE0 /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/trigger_p_o
add wave -noupdate /main/DUT/cnx_slave_out(0).ack add wave -noupdate -group ADC_CORE0 /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/acq_start_p_o
add wave -noupdate /main/DUT/cnx_slave_out(0).stall add wave -noupdate -group ADC_CORE0 /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/acq_stop_p_o
add wave -noupdate -radix hexadecimal /main/DUT/cnx_slave_out(0).dat add wave -noupdate -group ADC_CORE0 /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/acq_end_p_o
add wave -noupdate -divider {wb ddr0 addr} add wave -noupdate -group ADC_CORE0 -radix hexadecimal /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/trigger_tag_i
add wave -noupdate /main/DUT/cnx_master_out(6).cyc add wave -noupdate -group ADC_CORE0 /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/time_trig_i
add wave -noupdate /main/DUT/cnx_master_out(6).stb add wave -noupdate -group ADC_CORE0 /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/time_trig
add wave -noupdate /main/DUT/cnx_master_out(6).we add wave -noupdate -group TMP1 /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_time_trig_sync/*
add wave -noupdate -radix hexadecimal /main/DUT/cnx_master_out(6).adr add wave -noupdate -group TMP2 /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/*
add wave -noupdate -radix hexadecimal /main/DUT/cnx_master_out(6).dat add wave -noupdate -group TIMETAG -radix hexadecimal /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_timetag_core/*
add wave -noupdate /main/DUT/cnx_master_in(6).ack add wave -noupdate -group WB_VME /main/DUT/cnx_slave_in(0).cyc
add wave -noupdate -radix hexadecimal /main/DUT/cnx_master_in(6).dat add wave -noupdate -group WB_VME /main/DUT/cnx_slave_in(0).stb
add wave -noupdate -radix hexadecimal /main/DUT/ddr0_addr_cnt add wave -noupdate -group WB_VME /main/DUT/cnx_slave_in(0).we
add wave -noupdate -divider {wb ddr0 data} add wave -noupdate -group WB_VME -radix hexadecimal /main/DUT/cnx_slave_in(0).adr
add wave -noupdate /main/DUT/cnx_master_out(5).cyc add wave -noupdate -group WB_VME -radix hexadecimal /main/DUT/cnx_slave_in(0).dat
add wave -noupdate /main/DUT/cnx_master_out(5).stb add wave -noupdate -group WB_VME /main/DUT/cnx_slave_out(0).ack
add wave -noupdate /main/DUT/cnx_master_out(5).we add wave -noupdate -group WB_VME /main/DUT/cnx_slave_out(0).stall
add wave -noupdate -radix hexadecimal /main/DUT/cnx_master_out(5).adr add wave -noupdate -group WB_VME -radix hexadecimal /main/DUT/cnx_slave_out(0).dat
add wave -noupdate -radix hexadecimal /main/DUT/cnx_master_out(5).dat add wave -noupdate -group WB_DDR0 -divider {wb ddr0 addr}
add wave -noupdate /main/DUT/cnx_master_in(5).ack add wave -noupdate -group WB_DDR0 /main/DUT/cnx_master_out(6).cyc
add wave -noupdate -radix hexadecimal /main/DUT/cnx_master_in(5).dat add wave -noupdate -group WB_DDR0 /main/DUT/cnx_master_out(6).stb
add wave -noupdate /main/DUT/ddr0_wb_cyc_d add wave -noupdate -group WB_DDR0 /main/DUT/cnx_master_out(6).we
add wave -noupdate /main/DUT/ddr0_wb_cyc_fe add wave -noupdate -group WB_DDR0 -radix hexadecimal /main/DUT/cnx_master_out(6).adr
add wave -noupdate -divider {ddr0 ctrl wb1} add wave -noupdate -group WB_DDR0 -radix hexadecimal /main/DUT/cnx_master_out(6).dat
add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/wb_we_f_edge add wave -noupdate -group WB_DDR0 /main/DUT/cnx_master_in(6).ack
add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/wb_stb_f_edge add wave -noupdate -group WB_DDR0 -radix hexadecimal /main/DUT/cnx_master_in(6).dat
add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/wb_cyc_r_edge add wave -noupdate -group WB_DDR0 -radix hexadecimal /main/DUT/ddr0_addr_cnt
add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/wb_cyc_f_edge add wave -noupdate -group WB_DDR0 -divider {wb ddr0 data}
add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/wb_stall_o add wave -noupdate -group WB_DDR0 /main/DUT/cnx_master_out(5).cyc
add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/wb_data_o add wave -noupdate -group WB_DDR0 /main/DUT/cnx_master_out(5).stb
add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/wb_data_i add wave -noupdate -group WB_DDR0 /main/DUT/cnx_master_out(5).we
add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/wb_addr_i add wave -noupdate -group WB_DDR0 -radix hexadecimal /main/DUT/cnx_master_out(5).adr
add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/wb_addr_d add wave -noupdate -group WB_DDR0 -radix hexadecimal /main/DUT/cnx_master_out(5).dat
add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_wr_underrun_i add wave -noupdate -group WB_DDR0 /main/DUT/cnx_master_in(5).ack
add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_wr_mask_o add wave -noupdate -group WB_DDR0 -radix hexadecimal /main/DUT/cnx_master_in(5).dat
add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_wr_mask add wave -noupdate -group DDR_CTRL_B4 -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/wb_we_f_edge
add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_wr_full_i add wave -noupdate -group DDR_CTRL_B4 -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/wb_stb_f_edge
add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_wr_en add wave -noupdate -group DDR_CTRL_B4 -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/wb_cyc_r_edge
add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_wr_empty_i add wave -noupdate -group DDR_CTRL_B4 -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/wb_cyc_f_edge
add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_wr_data add wave -noupdate -group DDR_CTRL_B4 -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/wb_stall_o
add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_wr_count_i add wave -noupdate -group DDR_CTRL_B4 -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/wb_data_o
add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_rd_overflow_i add wave -noupdate -group DDR_CTRL_B4 -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/wb_data_i
add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_rd_full_i add wave -noupdate -group DDR_CTRL_B4 -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/wb_addr_i
add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_rd_error_i add wave -noupdate -group DDR_CTRL_B4 -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/wb_addr_d
add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_rd_en add wave -noupdate -group DDR_CTRL_B4 -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_wr_underrun_i
add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_rd_empty_i add wave -noupdate -group DDR_CTRL_B4 -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_wr_mask_o
add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_rd_data_i add wave -noupdate -group DDR_CTRL_B4 -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_wr_mask
add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_rd_count_i add wave -noupdate -group DDR_CTRL_B4 -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_wr_full_i
add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_cmd_instr add wave -noupdate -group DDR_CTRL_B4 -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_wr_en
add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_cmd_full_i add wave -noupdate -group DDR_CTRL_B4 -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_wr_empty_i
add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_cmd_en_r_edge add wave -noupdate -group DDR_CTRL_B4 -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_wr_data
add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_cmd_en add wave -noupdate -group DDR_CTRL_B4 -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_wr_count_i
add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_cmd_empty_i add wave -noupdate -group DDR_CTRL_B4 -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_rd_overflow_i
add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr add wave -noupdate -group DDR_CTRL_B4 -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_rd_full_i
add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_cmd_bl add wave -noupdate -group DDR_CTRL_B4 -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_rd_error_i
add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_burst_cnt add wave -noupdate -group DDR_CTRL_B4 -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_rd_en
add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/addr_shift add wave -noupdate -group DDR_CTRL_B4 -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_rd_empty_i
add wave -noupdate /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b/cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/MCB_SYSRST add wave -noupdate -group DDR_CTRL_B4 -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_rd_data_i
add wave -noupdate -divider {timetag core} add wave -noupdate -group DDR_CTRL_B4 -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_rd_count_i
add wave -noupdate -radix hexadecimal /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_timetag_core/* add wave -noupdate -group DDR_CTRL_B4 -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_cmd_instr
add wave -noupdate -group DDR_CTRL_B4 -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_cmd_full_i
add wave -noupdate -group DDR_CTRL_B4 -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_cmd_en_r_edge
add wave -noupdate -group DDR_CTRL_B4 -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_cmd_en
add wave -noupdate -group DDR_CTRL_B4 -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_cmd_empty_i
add wave -noupdate -group DDR_CTRL_B4 -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr
add wave -noupdate -group DDR_CTRL_B4 -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_cmd_bl
add wave -noupdate -group DDR_CTRL_B4 -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_burst_cnt
add wave -noupdate -group DDR_CTRL_B4 -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/addr_shift
add wave -noupdate -group DDR_CTRL_B4 /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b/cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/MCB_SYSRST
TreeUpdate [SetDefaultTree] TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {29753000 ps} 0} WaveRestoreCursors {{Cursor 1} {29753000 ps} 0}
configure wave -namecolwidth 454 configure wave -namecolwidth 454
......
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