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FMC ADC 100M 14b 4cha - Gateware
Commit 7577ea5e authored by mcattin's avatar mcattin
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Reorganise dirs. 

git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@62 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
parent fa979408
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Showing with 140 additions and 55 deletions
hdl/spec/rtl/Manifest.py
View file @ 7577ea5e
......@@ -5,8 +5,8 @@ files = [
modules = {
"local" : "../../adc/rtl",
"svn" : [ "http://svn.ohwr.org/DDRCONTROLLER",
"http://svn.ohwr.org/GENNUMCORE"],
"svn" : [ "http://svn.ohwr.org/ddr3-sp6-core/trunk/hdl/rtl",
"http://svn.ohwr.org/gn4124-core/trunk/hdl/gn4124core/rtl"],
"git" : "git://ohwr.org/hdl-core-lib/general-cores.git"}
fetchto="../ip_cores"
hdl/spec/ise_project/_xmsgs/pn_parser.xmsgs → hdl/spec/syn/_xmsgs/pn_parser.xmsgs
View file @ 7577ea5e
......@@ -8,6 +8,75 @@
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/ddr3_ctrl_core/hdl/spec/ip_cores/ddr_controller_bank3_64b/user_design/rtl/ddr_controller_bank3_64b.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/ddr3_ctrl_core/hdl/spec/ip_cores/ddr_controller_bank3_64b/user_design/rtl/iodrp_controller.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/ddr3_ctrl_core/hdl/spec/ip_cores/ddr_controller_bank3_64b/user_design/rtl/iodrp_mcb_controller.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/ddr3_ctrl_core/hdl/spec/ip_cores/ddr_controller_bank3_64b/user_design/rtl/mcb_raw_wrapper.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/ddr3_ctrl_core/hdl/spec/ip_cores/ddr_controller_bank3_64b/user_design/rtl/mcb_soft_calibration.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/ddr3_ctrl_core/hdl/spec/ip_cores/ddr_controller_bank3_64b/user_design/rtl/mcb_soft_calibration_top.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/ddr3_ctrl_core/hdl/spec/ip_cores/ddr_controller_bank3_64b/user_design/rtl/memc3_infrastructure.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/ddr3_ctrl_core/hdl/spec/ip_cores/ddr_controller_bank3_64b/user_design/rtl/memc3_wrapper.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/ddr3_ctrl_core/hdl/spec/rtl/ddr3_ctrl.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/ext_pulse_sync/ext_pulse_sync_rtl.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/fmc_adc_100Ms/hdl/spec/ip_cores/adc_serdes.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/fmc_adc_100Ms/hdl/spec/ip_cores/multishot_dpram.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/fmc_adc_100Ms/hdl/spec/ip_cores/test_dpram.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/fmc_adc_100Ms/hdl/spec/ip_cores/wb_ddr_fifo.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/fmc_adc_100Ms/hdl/spec/rtl/carrier_csr.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/fmc_adc_100Ms/hdl/spec/rtl/fmc_adc_100Ms_core.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/fmc_adc_100Ms/hdl/spec/rtl/fmc_adc_100Ms_csr.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/fmc_adc_100Ms/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/monostable/monostable_rtl.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/utils/utils_pkg.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/wb_i2c_master/rtl/vhdl/i2c_master_bit_ctrl.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/wb_i2c_master/rtl/vhdl/i2c_master_byte_ctrl.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/wb_i2c_master/rtl/vhdl/i2c_master_top.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1574" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;/home/mcattin/projects/wb_spi_master/spi_clgen.v\&quot; into library work</arg>
</msg>
......
hdl/spec/ise_project/iseconfig/spec_fmc_adc_100Ms.projectmgr → hdl/spec/syn/iseconfig/spec_fmc_adc_100Ms.projectmgr
View file @ 7577ea5e
......@@ -18,15 +18,16 @@
<ClosedNode>/spec_top_fmc_adc_100Ms - rtl/cmp_fmc_adc_100Ms_core - fmc_adc_100Ms_core - rtl</ClosedNode>
<ClosedNode>/spec_top_fmc_adc_100Ms - rtl/cmp_fmc_i2c - i2c_master_top - structural</ClosedNode>
<ClosedNode>/spec_top_fmc_adc_100Ms - rtl/cmp_fmc_spi - wb_spi_master</ClosedNode>
<ClosedNode>/spec_top_fmc_adc_100Ms - rtl/cmp_gn4124_core - gn4124_core - rtl</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem>cmp_clk_in - serdes_1_to_n_clk_pll_s2_diff - arch_serdes_1_to_n_clk_pll_s2_diff (/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/serdes_1_to_n_clk_pll_s2_diff.vhd)</SelectedItem>
<SelectedItem>spec_top_fmc_adc_100Ms - rtl (/home/mcattin/projects/fmc_adc_100Ms/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd)</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >3</ScrollbarPosition>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000035c000000020000000000000000000000000000000064ffffffff0000008100000000000000020000035c0000000100000000000000000000000100000000</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000004a5000000020000000000000000000000000000000064ffffffff000000810000000000000002000004a50000000100000000000000000000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>cmp_clk_in - serdes_1_to_n_clk_pll_s2_diff - arch_serdes_1_to_n_clk_pll_s2_diff (/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/serdes_1_to_n_clk_pll_s2_diff.vhd)</CurrentItem>
<CurrentItem>spec_top_fmc_adc_100Ms - rtl (/home/mcattin/projects/fmc_adc_100Ms/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd)</CurrentItem>
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >
<ClosedNodes>
......@@ -46,20 +47,20 @@
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000415000000010000000100000000000000000000000064ffffffff000000810000000000000001000004150000000100000000</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000001b3000000010000000100000000000000000000000064ffffffff000000810000000000000001000001b30000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>Add Existing Source</CurrentItem>
</ItemView>
<ItemView guiview="File" >
<ClosedNodes/>
<SelectedItems>
<SelectedItem>gn4124_core_pkg_s6.vhd</SelectedItem>
<SelectedItem>../../../../ddr3_ctrl_core/hdl/spec/ip_cores/ddr_controller_bank3_64b/user_design/rtl/memc3_wrapper.vhd</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000507000000040101000100000000000000000000000064ffffffff0000008100000000000000040000033c0000000100000000000000d60000000100000000000000840000000100000000000000710000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>gn4124_core_pkg_s6.vhd</CurrentItem>
<CurrentItem>../../../../ddr3_ctrl_core/hdl/spec/ip_cores/ddr_controller_bank3_64b/user_design/rtl/memc3_wrapper.vhd</CurrentItem>
</ItemView>
<ItemView guiview="Library" >
<ClosedNodes>
......@@ -83,7 +84,7 @@
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000287000000010000000100000000000000000000000064ffffffff000000810000000000000001000002870000000100000000</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000415000000010000000100000000000000000000000064ffffffff000000810000000000000001000004150000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>Add Existing Source</CurrentItem>
</ItemView>
......@@ -107,7 +108,7 @@
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000000000000000000039e000000010000000100000000000000000000000064ffffffff0000008100000000000000010000039e0000000100000000</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000224000000010000000100000000000000000000000064ffffffff000000810000000000000001000002240000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>Add Existing Source</CurrentItem>
</ItemView>
......@@ -129,7 +130,7 @@
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000000000000000000013f000000010000000100000000000000000000000064ffffffff0000008100000000000000010000013f0000000100000000</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000000000000000000014a000000010000000100000000000000000000000064ffffffff0000008100000000000000010000014a0000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>Add Existing Source</CurrentItem>
</ItemView>
......
hdl/spec/ise_project/spec_fmc_adc_100Ms.gise → hdl/spec/syn/spec_fmc_adc_100Ms.gise
View file @ 7577ea5e
......@@ -140,19 +140,12 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms.lso"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms.ngc"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms.ngr"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms.prj"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms.stx"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms.syr"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms.xst"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms_xst.xrpt"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
<transform xil_pn:end_ts="1303288526" xil_pn:in_ck="2162529744943951648" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-4337831395208791850" xil_pn:start_ts="1303288525">
<status xil_pn:value="SuccessfullyRun"/>
......@@ -163,6 +156,7 @@
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputRemoved"/>
......
hdl/spec/ise_project/spec_fmc_adc_100Ms.xise → hdl/spec/syn/spec_fmc_adc_100Ms.xise
View file @ 7577ea5e
......@@ -15,22 +15,10 @@
<version xil_pn:ise_version="12.2" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="../../../../GN4124_core/hdl/gn4124core/rtl/gn4124_core_pkg_s6.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../../../../GN4124_core/hdl/gn4124core/rtl/gn4124_core_s6.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../../../../GN4124_core/hdl/gn4124core/rtl/l2p_ser_s6.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../../../../GN4124_core/hdl/gn4124core/rtl/p2l_des_s6.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../../../../GN4124_core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../../../GN4124_core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../../../GN4124_core/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../../../GN4124_core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../../../GN4124_core/hdl/gn4124core/rtl/wbmaster32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
......@@ -59,22 +47,10 @@
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../../../../GN4124_core/hdl/gn4124core/rtl/serdes_n_to_1_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../../../../GN4124_core/hdl/gn4124core/rtl/serdes_n_to_1_s2_se.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../../../../GN4124_core/hdl/gn4124core/rtl/serdes_1_to_n_clk_pll_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../../../../GN4124_core/hdl/gn4124core/rtl/serdes_1_to_n_data_s2_se.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../../../../GN4124_core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../../../GN4124_core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../../../GN4124_core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../../../GN4124_core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../../../ddr3_ctrl_core/hdl/spec/rtl/ddr3_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
......
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