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FMC ADC 100M 14b 4cha - Gateware
Commit 686966d0 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: eliminated local monostable in favor of general-cores pulse extender

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hdl/adc/rtl/fmc_adc_100Ms_core.vhd
View file @ 686966d0
......@@ -179,23 +179,6 @@ architecture rtl of fmc_adc_100Ms_core is
);
end component offset_gain_s;
component monostable
generic(
g_INPUT_POLARITY : std_logic := '1'; --! trigger_i polarity
--! ('0'=negative, 1=positive)
g_OUTPUT_POLARITY : std_logic := '1'; --! pulse_o polarity
--! ('0'=negative, 1=positive)
g_OUTPUT_RETRIG : boolean := FALSE; --! Retriggerable output monostable
g_OUTPUT_LENGTH : natural := 1 --! pulse_o lenght (in clk_i ticks)
);
port (
rst_n_i : in std_logic; --! Reset (active low)
clk_i : in std_logic; --! Clock
trigger_i : in std_logic; --! Trigger input pulse
pulse_o : out std_logic --! Monostable output pulse
);
end component monostable;
------------------------------------------------------------------------------
-- Constants declaration
------------------------------------------------------------------------------
......@@ -399,35 +382,25 @@ begin
------------------------------------------------------------------------------
-- LEDs
------------------------------------------------------------------------------
cmp_acq_led_monostable : monostable
generic map(
g_INPUT_POLARITY => '1',
g_OUTPUT_POLARITY => '1',
g_OUTPUT_RETRIG => TRUE,
g_OUTPUT_LENGTH => 12500000
)
port map(
rst_n_i => sys_rst_n_i,
clk_i => sys_clk_i,
trigger_i => samples_wr_en,
pulse_o => acq_led
);
cmp_acq_led: gc_extend_pulse
generic map (
g_width => 12500000)
port map (
clk_i => sys_clk_i,
rst_n_i => sys_rst_n_i,
pulse_i => samples_wr_en,
extended_o => acq_led);
gpio_led_acq_o <= acq_led or acq_led_man;
cmp_trig_led_monostable : monostable
generic map(
g_INPUT_POLARITY => '1',
g_OUTPUT_POLARITY => '1',
g_OUTPUT_RETRIG => TRUE,
g_OUTPUT_LENGTH => 12500000
)
port map(
rst_n_i => sys_rst_n_i,
clk_i => sys_clk_i,
trigger_i => acq_trig,
pulse_o => trig_led
);
cmp_trig_led: gc_extend_pulse
generic map (
g_width => 12500000)
port map (
clk_i => sys_clk_i,
rst_n_i => sys_rst_n_i,
pulse_i => acq_trig,
extended_o => trig_led);
gpio_led_trig_o <= trig_led or trig_led_man;
......
hdl/ip_cores/monostable/monostable_rtl.vhd deleted 100755 → 0
View file @ a16adcbf
--=============================================================================
-- @file monostable_rtl.vhd
--=============================================================================
--! Standard library
library IEEE;
--! Standard packages
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
--! Specific packages
-------------------------------------------------------------------------------
-- --
-- CERN, BE-CO-HT, Monostable
-- --
-------------------------------------------------------------------------------
--
-- Unit name: Monostable (monostable_rtl)
--
--! @brief Monostable
--!
--
--! @author Matthieu Cattin (matthieu dot cattin at cern dot ch)
--
--! @date 27\10\2009
--
--! @version v1.0
--
--! @details
--!
--! <b>Dependencies:</b>\n
--!
--! <b>References:</b>\n
--!
--!
--! <b>Modified by:</b>\n
--! Author:
-------------------------------------------------------------------------------
--! \n\n<b>Last changes:</b>\n
--! 27.10.2009 mcattin Creation from ext_pulse_sync_rtl.vhd
--!
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
--! @todo
--
-------------------------------------------------------------------------------
--=============================================================================
--! Entity declaration for Monostable
--=============================================================================
entity monostable is
generic(
g_INPUT_POLARITY : std_logic := '1'; --! trigger_i polarity
--! ('0'=negative, 1=positive)
g_OUTPUT_POLARITY : std_logic := '1'; --! pulse_o polarity
--! ('0'=negative, 1=positive)
g_OUTPUT_RETRIG : boolean := false; --! Retriggerable output monostable
g_OUTPUT_LENGTH : natural := 1 --! pulse_o lenght (in clk_i ticks)
);
port (
rst_n_i : in std_logic; --! Reset (active low)
clk_i : in std_logic; --! Clock
trigger_i : in std_logic; --! Trigger input pulse
pulse_o : out std_logic --! Monostable output pulse
);
end entity monostable;
--=============================================================================
--! Architecture declaration Monostable
--=============================================================================
architecture rtl of monostable is
--! log2 function
function log2_ceil(N : natural) return positive is
begin
if N <= 2 then
return 1;
elsif N mod 2 = 0 then
return 1 + log2_ceil(N/2);
else
return 1 + log2_ceil((N+1)/2);
end if;
end;
--! FFs for monostable start
signal s_trigger_d : std_logic_vector(1 downto 0) := (others => '0');
--! Output pulse monostable counter
signal s_monostable_cnt : unsigned(log2_ceil(g_OUTPUT_LENGTH) downto 0) := (others => '0');
--! Output pulse for readback
signal s_output_pulse : std_logic := '0';
--=============================================================================
--! Architecture begin
--=============================================================================
begin
--*****************************************************************************
-- Begin of p_trigger
--! Process: FF to generate monostable start pulse
--*****************************************************************************
p_trigger : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
s_trigger_d <= (others => '0');
else
if trigger_i = g_INPUT_POLARITY then
s_trigger_d(0) <= '1';
else
s_trigger_d(0) <= '0';
end if;
s_trigger_d(1) <= s_trigger_d(0);
end if;
end if;
end process p_trigger;
--*****************************************************************************
-- Begin of p_monostable
--! Process: Monostable to generate output pulse
--*****************************************************************************
p_monostable : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
s_monostable_cnt <= (others => '0');
s_output_pulse <= not(g_OUTPUT_POLARITY);
elsif ((not(g_OUTPUT_RETRIG)
and ((s_trigger_d(0) and not(s_trigger_d(1))) = '1')
and (s_output_pulse /= g_OUTPUT_POLARITY)) -- non-retriggerable
or (g_OUTPUT_RETRIG and (s_trigger_d(0) = '1'))) then -- retriggerable
s_monostable_cnt <= to_unsigned(g_OUTPUT_LENGTH, s_monostable_cnt'length) - 1;
s_output_pulse <= g_OUTPUT_POLARITY;
elsif s_monostable_cnt = to_unsigned(0, s_monostable_cnt'length) then
s_output_pulse <= not(g_OUTPUT_POLARITY);
else
s_monostable_cnt <= s_monostable_cnt - 1;
end if;
end if;
end process p_monostable;
pulse_o <= s_output_pulse;
end architecture rtl;
--=============================================================================
--! Architecture end
--=============================================================================
hdl/ip_cores/monostable/monostable_tb.vhd deleted 100755 → 0
View file @ a16adcbf
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:59:19 10/22/2009
-- Design Name:
-- Module Name: C:/mcattin/fpga_design/cvorb_cvorg/sources/monostable_tb.vhd
-- Project Name: cvorb_v3
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: monostable
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity monostable_tb is
end monostable_tb;
architecture behavior of monostable_tb is
-- Component Declaration for the Unit Under Test (UUT)
component monostable
generic(
g_INPUT_POLARITY : std_logic := '1'; --! pulse_i polarity
--! ('0'=negative, 1=positive)
g_OUTPUT_POLARITY : std_logic := '1'; --! pulse_o polarity
--! ('0'=negative, 1=positive)
g_OUTPUT_RETRIG : boolean := FALSE; --!
g_OUTPUT_LENGTH : natural := 1 --! pulse_o lenght (in clk_i ticks)
);
port(
rst_n_i : in std_logic;
clk_i : in std_logic;
trigger_i : in std_logic;
pulse_o : out std_logic
);
end component;
--Inputs
signal rst_n_i : std_logic := '0';
signal clk_i : std_logic := '0';
signal trigger_i : std_logic := '0';
--Outputs
signal pulse_o : std_logic;
-- Clock period definitions
constant clk_i_period : time := 25 us;
begin
-- Instantiate the Unit Under Test (UUT)
uut : monostable
generic map(
g_INPUT_POLARITY => '1',
g_OUTPUT_POLARITY => '0',
g_OUTPUT_RETRIG => FALSE,
g_OUTPUT_LENGTH => 10
)
port map (
rst_n_i => rst_n_i,
clk_i => clk_i,
trigger_i => trigger_i,
pulse_o => pulse_o
);
-- Clock process definitions
clk_i_process : process
begin
clk_i <= '0';
wait for 12.5 ns;
clk_i <= '1';
wait for 12.5 ns;
end process;
-- Stimulus process
stim_proc : process
begin
-- hold reset state for 1 us.
rst_n_i <= '0';
wait for 1 us;
rst_n_i <= '1';
wait for 100 ns;
wait until rising_edge(clk_i);
trigger_i <= '1';
wait until rising_edge(clk_i);
--wait for 500 ns;
trigger_i <= '0';
wait for 200 ns;
wait until rising_edge(clk_i);
trigger_i <= '1';
wait until rising_edge(clk_i);
trigger_i <= '0';
wait;
end process;
end;
hdl/spec/syn/Manifest.py
View file @ 686966d0
......@@ -13,8 +13,7 @@ files = [
"../../ip_cores/adc_sync_fifo.ngc",
"../../ip_cores/multishot_dpram.ngc",
"../../ip_cores/wb_ddr_fifo.ngc",
"../../ip_cores/adc_serdes.vhd",
"../../ip_cores/monostable/monostable_rtl.vhd"]
"../../ip_cores/adc_serdes.vhd"]
modules = { "local" : ["../rtl",
"../../adc/rtl",
......
hdl/spec/testbench/top/Manifest.py
View file @ 686966d0
......@@ -9,8 +9,7 @@ include_dirs=["../include","gn4124_bfm", "ddr3"]
files = [
"main.sv",
"ddr3/ddr3.v",
"../../../ip_cores/adc_serdes.vhd",
"../../../ip_cores/monostable/monostable_rtl.vhd"]
"../../../ip_cores/adc_serdes.vhd"]
modules = { "local" : [ "../../rtl",
"gn4124_bfm",
......
hdl/svec/sim/testbench/Manifest.py
View file @ 686966d0
......@@ -9,8 +9,7 @@ files = [ "main.sv",
"../../../ip_cores/adc_sync_fifo.vhd",
"../../../ip_cores/multishot_dpram.vhd",
"../../../ip_cores/wb_ddr_fifo.vhd",
"../../../ip_cores/adc_serdes.vhd",
"../../../ip_cores/monostable/monostable_rtl.vhd"]
"../../../ip_cores/adc_serdes.vhd"]
modules = { "local" : [ "../../rtl",
"../2048Mb_ddr3",
......
hdl/svec/syn/Manifest.py
View file @ 686966d0
......@@ -13,8 +13,7 @@ files = [
"../../ip_cores/adc_sync_fifo.ngc",
"../../ip_cores/multishot_dpram.ngc",
"../../ip_cores/wb_ddr_fifo.ngc",
"../../ip_cores/adc_serdes.vhd",
"../../ip_cores/monostable/monostable_rtl.vhd"]
"../../ip_cores/adc_serdes.vhd"]
modules = { "local" : ["../rtl",
"../../adc/rtl",
......
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