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FMC ADC 100M 14b 4cha - Gateware
Commit 4f7b5076 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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[svec] post-Convention cleanup

parent ee86f701
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hdl/cheby/svec_ref_fmc_adc_100Ms_mmap.cheby
View file @ 4f7b5076
memory-map:
name: spec_ref_fmc_adc_100m_mmap
name: svec_ref_fmc_adc_100m_mmap
bus: wb-32-be
description: SPEC FMC-ADC-100M memory map
size: 0x8000
......
hdl/cheby/svec_ref_fmc_adc_100Ms_mmap.vhd
View file @ 4f7b5076
......@@ -6,7 +6,7 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
entity spec_ref_fmc_adc_100m_mmap is
entity svec_ref_fmc_adc_100m_mmap is
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
......@@ -25,9 +25,9 @@ entity spec_ref_fmc_adc_100m_mmap is
fmc2_adc_mezzanine_i : in t_wishbone_master_in;
fmc2_adc_mezzanine_o : out t_wishbone_master_out
);
end spec_ref_fmc_adc_100m_mmap;
end svec_ref_fmc_adc_100m_mmap;
architecture syn of spec_ref_fmc_adc_100m_mmap is
architecture syn of svec_ref_fmc_adc_100m_mmap is
signal rd_int : std_logic;
signal wr_int : std_logic;
signal rd_ack_int : std_logic;
......
svec @ ce6b58a3
Subproject commit 8aa8d699f30c3ed1d02e3aa96c00492fdb0e2051
Subproject commit ce6b58a38c12da91494dafc2a77cce6f16c0762f
hdl/testbench/include/svec_ref_fmc_adc_100Ms_mmap.v
View file @ 4f7b5076
`define SPEC_REF_FMC_ADC_100M_MMAP_SIZE 32768
`define ADDR_SPEC_REF_FMC_ADC_100M_MMAP_METADATA 'h2000
`define SPEC_REF_FMC_ADC_100M_MMAP_METADATA_SIZE 64
`define ADDR_SPEC_REF_FMC_ADC_100M_MMAP_FMC1_ADC_MEZZANINE 'h4000
`define SPEC_REF_FMC_ADC_100M_MMAP_FMC1_ADC_MEZZANINE_SIZE 8192
`define ADDR_SPEC_REF_FMC_ADC_100M_MMAP_FMC2_ADC_MEZZANINE 'h6000
`define SPEC_REF_FMC_ADC_100M_MMAP_FMC2_ADC_MEZZANINE_SIZE 8192
`define SVEC_REF_FMC_ADC_100M_MMAP_SIZE 32768
`define ADDR_SVEC_REF_FMC_ADC_100M_MMAP_METADATA 'h2000
`define SVEC_REF_FMC_ADC_100M_MMAP_METADATA_SIZE 64
`define ADDR_SVEC_REF_FMC_ADC_100M_MMAP_FMC1_ADC_MEZZANINE 'h4000
`define SVEC_REF_FMC_ADC_100M_MMAP_FMC1_ADC_MEZZANINE_SIZE 8192
`define ADDR_SVEC_REF_FMC_ADC_100M_MMAP_FMC2_ADC_MEZZANINE 'h6000
`define SVEC_REF_FMC_ADC_100M_MMAP_FMC2_ADC_MEZZANINE_SIZE 8192
hdl/testbench/svec_ref_design/.gitignore
View file @ 4f7b5076
......@@ -4,3 +4,4 @@ transcript
vsim.wlf
NullFile
modelsim.ini
buildinfo_pkg.vhd
hdl/testbench/svec_ref_design/Manifest.py
View file @ 4f7b5076
board = "svec"
sim_tool = "modelsim"
top_module = "main"
sim_top = "main"
action = "simulation"
target = "xilinx"
syn_device = "xc6slx150t"
vcom_opt = "-93 -mixedsvvh"
fetchto = "../../ip_cores"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto="../../ip_cores"
include_dirs = [
"../include",
......@@ -19,19 +22,19 @@ include_dirs = [
files = [
"main.sv",
"synthesis_descriptor.vhd",
"buildinfo_pkg.vhd",
]
modules = {
"local" : [
"../../top/svec_ref_design",
],
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git",
"git://ohwr.org/hdl-core-lib/wr-cores.git",
"git://ohwr.org/hdl-core-lib/ddr3-sp6-core.git",
"git://ohwr.org/hdl-core-lib/vme64x-core.git",
],
}
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
ctrls = ["bank4_64b_32b", "bank5_64b_32b"]
hdl/testbench/svec_ref_design/main.sv
View file @ 4f7b5076
......@@ -5,9 +5,8 @@
`include "fmc_adc_100Ms_csr.v"
`define VME_OFFSET 'h80000000
`define ADC_OFFSET 'h2000
`define ADC_OFFSET 'h4000
`define SDB_ADDR `VME_OFFSET + 0
`define CSR_BASE `VME_OFFSET + `ADC_OFFSET + 'h1000
`define OWC_BASE `VME_OFFSET + `ADC_OFFSET + 'h1700
`define TAG_BASE `VME_OFFSET + `ADC_OFFSET + 'h1900
......@@ -62,8 +61,7 @@ module main;
svec_ref_fmc_adc_100Ms
#(
.g_SIMULATION(1),
.g_CALIB_SOFT_IP("FALSE")
.g_SIMULATION(1)
)
DUT
(
......@@ -83,7 +81,7 @@ module main;
.adc_outb_p_i (adc_dat_even),
.adc_outb_n_i (~adc_dat_even),
.vme_as_n_i (VME_AS_n),
.vme_rst_n_i (VME_RST_n),
.vme_sysreset_n_i (VME_RST_n),
.vme_write_n_i (VME_WRITE_n),
.vme_am_i (VME_AM),
.vme_ds_n_i (VME_DS_n),
......@@ -105,27 +103,50 @@ module main;
.vme_data_oe_n_o (VME_DATA_OE_N),
.vme_addr_dir_o (VME_ADDR_DIR),
.vme_addr_oe_n_o (VME_ADDR_OE_N),
.ddr_reset_n_o (ddr_reset_n),
.ddr_ck_p_o (ddr_ck_p),
.ddr_ck_n_o (ddr_ck_n),
.ddr_cke_o (ddr_cke),
.ddr_ras_n_o (ddr_ras_n),
.ddr_cas_n_o (ddr_cas_n),
.ddr_we_n_o (ddr_we_n),
.ddr_udm_o (ddr_dm[1]),
.ddr_ldm_o (ddr_dm[0]),
.ddr_ba_o (ddr_ba),
.ddr_a_o (ddr_a),
.ddr_dq_b (ddr_dq),
.ddr_udqs_p_b (ddr_dqs_p[1]),
.ddr_udqs_n_b (ddr_dqs_n[1]),
.ddr_ldqs_p_b (ddr_dqs_p[0]),
.ddr_ldqs_n_b (ddr_dqs_n[0]),
.ddr_odt_o (ddr_odt),
.ddr_rzq_b (ddr_rzq)
.ddr4_reset_n_o (ddr_reset_n[0]),
.ddr4_ck_p_o (ddr_ck_p[0]),
.ddr4_ck_n_o (ddr_ck_n[0]),
.ddr4_cke_o (ddr_cke[0]),
.ddr4_ras_n_o (ddr_ras_n[0]),
.ddr4_cas_n_o (ddr_cas_n[0]),
.ddr4_we_n_o (ddr_we_n[0]),
.ddr4_udm_o (ddr_dm[1][0]),
.ddr4_ldm_o (ddr_dm[0][0]),
.ddr4_ba_o (ddr_ba[2:0]),
.ddr4_a_o (ddr_a[13:0]),
.ddr4_dq_b (ddr_dq[15:0]),
.ddr4_udqs_p_b (ddr_dqs_p[1][0]),
.ddr4_udqs_n_b (ddr_dqs_n[1][0]),
.ddr4_ldqs_p_b (ddr_dqs_p[0][0]),
.ddr4_ldqs_n_b (ddr_dqs_n[0][0]),
.ddr4_odt_o (ddr_odt[0]),
.ddr4_rzq_b (ddr_rzq[0]),
.ddr5_reset_n_o (ddr_reset_n[1]),
.ddr5_ck_p_o (ddr_ck_p[1]),
.ddr5_ck_n_o (ddr_ck_n[1]),
.ddr5_cke_o (ddr_cke[1]),
.ddr5_ras_n_o (ddr_ras_n[1]),
.ddr5_cas_n_o (ddr_cas_n[1]),
.ddr5_we_n_o (ddr_we_n[1]),
.ddr5_udm_o (ddr_dm[1][1]),
.ddr5_ldm_o (ddr_dm[0][1]),
.ddr5_ba_o (ddr_ba[5:3]),
.ddr5_a_o (ddr_a[27:14]),
.ddr5_dq_b (ddr_dq[31:16]),
.ddr5_udqs_p_b (ddr_dqs_p[1][1]),
.ddr5_udqs_n_b (ddr_dqs_n[1][1]),
.ddr5_ldqs_p_b (ddr_dqs_p[0][1]),
.ddr5_ldqs_n_b (ddr_dqs_n[0][1]),
.ddr5_odt_o (ddr_odt[1]),
.ddr5_rzq_b (ddr_rzq[1])
);
ddr3
ddr3 #
(
.DEBUG(0),
.check_strict_timing(0),
.check_strict_mrbits(0)
)
cmp_ddr0
(
.rst_n (ddr_reset_n[0]),
......@@ -142,10 +163,16 @@ module main;
.dq (ddr_dq[15:0]),
.dqs ({ddr_dqs_p[1][0],ddr_dqs_p[0][0]}),
.dqs_n ({ddr_dqs_n[1][0],ddr_dqs_n[0][0]}),
.odt (ddr_odt[0])
.odt (ddr_odt[0]),
.tdqs_n ()
);
ddr3
ddr3 #
(
.DEBUG(0),
.check_strict_timing(0),
.check_strict_mrbits(0)
)
cmp_ddr1
(
.rst_n (ddr_reset_n[1]),
......@@ -162,7 +189,8 @@ module main;
.dq (ddr_dq[31:16]),
.dqs ({ddr_dqs_p[1][1],ddr_dqs_p[0][1]}),
.dqs_n ({ddr_dqs_n[1][1],ddr_dqs_n[0][1]}),
.odt (ddr_odt[1])
.odt (ddr_odt[1]),
.tdqs_n ()
);
int adc_div = 0;
......@@ -233,6 +261,7 @@ module main;
acc.set_default_modifiers(A32 | D32 | SINGLE);
endtask // init_vme64x_core
task adc_status_print (input uint64_t val);
string msg;
msg = $sformatf ("<%t> ADC STATUS: FSM_STATE=%0d, PLL_LOCKED=%0d, PLL_SYNCED=%0d, CFG_OK=%0d",
......@@ -262,18 +291,6 @@ module main;
#1us;
expected = 'h5344422d;
acc.read(`SDB_ADDR, val);
if (val != expected)
$fatal (1, "Unable to detect SDB header at offset 0x%8x (got 0x%8x, expected 0x%8x).",
`SDB_ADDR, val , expected);
expected = 'h5344422d;
acc.read(`ADC_OFFSET+`SDB_ADDR, val);
if (val != expected)
$fatal (1, "Unable to detect SDB header at offset 0x%8x (got 0x%8x, expected 0x%8x).",
`ADC_OFFSET+`SDB_ADDR, val , expected);
expected = 'h19;
acc.read(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_STA, val);
if (val != expected)
......@@ -383,7 +400,7 @@ module main;
// set time trigger
acc.write(`TAG_BASE + 'h0c, 'h00000032); // timetag core seconds high
acc.write(`TAG_BASE + 'h10, 'h00005a34); // timetag core seconds low
acc.write(`TAG_BASE + 'h14, 'h00001000); // timetag core ticks
acc.write(`TAG_BASE + 'h14, 'h00001100); // timetag core ticks
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_PRE_SAMPLES, 'h00000010);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_POST_SAMPLES, 'h00000080);
......@@ -432,5 +449,17 @@ module main;
end
initial begin
// Silence Xilinx unisim DSP48A1 warnings about invalid OPMODE
force DUT.inst_svec_base.gen_wr.cmp_xwrc_board_svec.cmp_board_common.cmp_xwr_core.
WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
multiplier.D1.OPMODE_dly = 0;
force DUT.inst_svec_base.gen_wr.cmp_xwrc_board_svec.cmp_board_common.cmp_xwr_core.
WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
multiplier.D2.OPMODE_dly = 0;
force DUT.inst_svec_base.gen_wr.cmp_xwrc_board_svec.cmp_board_common.cmp_xwr_core.
WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
multiplier.D3.OPMODE_dly = 0;
end // initial begin
endmodule // main
hdl/top/svec_ref_design/svec_carrier_csr.cheby deleted 100644 → 0
View file @ ee86f701
memory-map:
bus: wb-32-be
name: svec_carrier_csr
description: SVEC carrier control and status registers
comment: |
Wishbone slave for control and status registers related to the SVEC FMC carrier
x-hdl:
busgroup: True
iogroup: carrier_csr
children:
- reg:
name: carrier
address: 0x00000000
width: 32
access: ro
description: Carrier type and PCB version
children:
- field:
name: pcb_rev
range: 4-0
description: PCB revision
comment: |
Binary coded PCB layout revision.
- field:
name: reserved
range: 15-5
description: Reserved register
comment: |
Ignore on read, write with 0's.
- field:
name: type
range: 31-16
description: Carrier type
comment: |
Carrier type identifier
1 = SPEC
2 = SVEC
3 = VFC
4 = SPEXI
- reg:
name: stat
address: 0x00000004
width: 32
access: ro
description: Status
children:
- field:
name: fmc0_pres
range: 0
description: FMC 1 presence
comment: |
0: FMC slot 1 is populated
1: FMC slot 1 is not populated.
- field:
name: fmc1_pres
range: 1
description: FMC 2 presence
comment: |
0: FMC slot 2 is populated
1: FMC slot 2 is not populated.
- field:
name: sys_pll_lck
range: 2
description: System clock PLL status
comment: |
0: not locked
1: locked.
- field:
name: ddr0_cal_done
range: 3
description: DDR3 bank 4 calibration status
comment: |
0: not done
1: done.
- field:
name: ddr1_cal_done
range: 4
description: DDR3 bank 5 calibration status
comment: |
0: not done
1: done.
- reg:
name: ctrl
address: 0x00000008
width: 32
access: rw
description: Control
children:
- field:
name: fp_leds_man
range: 15-0
description: Front panel LED manual control
comment: |
Height front panel LED, two bits per LED.
00 = OFF
01 = Green
10 = Red
11 = Orange
- reg:
name: rst
address: 0x0000000c
width: 32
access: wo
description: Reset Register
comment: |
Controls software reset of the mezzanines including the ddr interface and the time-tagging core.
children:
- field:
name: fmc0
range: 0
description: State of the FMC 1 reset line
comment: |
write 0: Normal FMC operation
write 1: FMC is held in reset
- field:
name: fmc1
range: 1
description: State of the FMC 2 reset line
comment: |
write 0: Normal FMC operation
write 1: FMC is held in reset
hdl/top/svec_ref_design/svec_carrier_csr.vhd deleted 100644 → 0
View file @ ee86f701
-- Do not edit; this file was generated by Cheby using these options:
-- -i svec_carrier_csr.cheby --gen-hdl=svec_carrier_csr.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
package svec_carrier_csr_pkg is
type t_carrier_csr_master_out is record
ctrl_fp_leds_man : std_logic_vector(15 downto 0);
rst_fmc0 : std_logic;
rst_fmc1 : std_logic;
end record t_carrier_csr_master_out;
subtype t_carrier_csr_slave_in is t_carrier_csr_master_out;
type t_carrier_csr_slave_out is record
carrier_pcb_rev : std_logic_vector(4 downto 0);
carrier_reserved : std_logic_vector(10 downto 0);
carrier_type : std_logic_vector(15 downto 0);
stat_fmc0_pres : std_logic;
stat_fmc1_pres : std_logic;
stat_sys_pll_lck : std_logic;
stat_ddr0_cal_done : std_logic;
stat_ddr1_cal_done : std_logic;
end record t_carrier_csr_slave_out;
subtype t_carrier_csr_master_in is t_carrier_csr_slave_out;
end svec_carrier_csr_pkg;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
use work.svec_carrier_csr_pkg.all;
entity svec_carrier_csr is
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out;
-- Wires and registers
carrier_csr_i : in t_carrier_csr_master_in;
carrier_csr_o : out t_carrier_csr_master_out
);
end svec_carrier_csr;
architecture syn of svec_carrier_csr is
signal rd_int : std_logic;
signal wr_int : std_logic;
signal rd_ack_int : std_logic;
signal wr_ack_int : std_logic;
signal wb_en : std_logic;
signal ack_int : std_logic;
signal wb_rip : std_logic;
signal wb_wip : std_logic;
signal ctrl_fp_leds_man_reg : std_logic_vector(15 downto 0);
signal rst_fmc0_reg : std_logic;
signal rst_fmc1_reg : std_logic;
signal reg_rdat_int : std_logic_vector(31 downto 0);
signal rd_ack1_int : std_logic;
begin
-- WB decode signals
wb_en <= wb_i.cyc and wb_i.stb;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wb_rip <= '0';
else
wb_rip <= (wb_rip or (wb_en and not wb_i.we)) and not rd_ack_int;
end if;
end if;
end process;
rd_int <= (wb_en and not wb_i.we) and not wb_rip;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wb_wip <= '0';
else
wb_wip <= (wb_wip or (wb_en and wb_i.we)) and not wr_ack_int;
end if;
end if;
end process;
wr_int <= (wb_en and wb_i.we) and not wb_wip;
ack_int <= rd_ack_int or wr_ack_int;
wb_o.ack <= ack_int;
wb_o.stall <= not ack_int and wb_en;
wb_o.rty <= '0';
wb_o.err <= '0';
-- Assign outputs
carrier_csr_o.ctrl_fp_leds_man <= ctrl_fp_leds_man_reg;
carrier_csr_o.rst_fmc0 <= rst_fmc0_reg;
carrier_csr_o.rst_fmc1 <= rst_fmc1_reg;
-- Process for write requests.
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wr_ack_int <= '0';
ctrl_fp_leds_man_reg <= "0000000000000000";
rst_fmc0_reg <= '0';
rst_fmc1_reg <= '0';
else
wr_ack_int <= '0';
case wb_i.adr(3 downto 2) is
when "00" =>
-- Register carrier
when "01" =>
-- Register stat
when "10" =>
-- Register ctrl
if wr_int = '1' then
ctrl_fp_leds_man_reg <= wb_i.dat(15 downto 0);
end if;
wr_ack_int <= wr_int;
when "11" =>
-- Register rst
if wr_int = '1' then
rst_fmc0_reg <= wb_i.dat(0);
rst_fmc1_reg <= wb_i.dat(1);
end if;
wr_ack_int <= wr_int;
when others =>
wr_ack_int <= wr_int;
end case;
end if;
end if;
end process;
-- Process for registers read.
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
rd_ack1_int <= '0';
else
reg_rdat_int <= (others => '0');
case wb_i.adr(3 downto 2) is
when "00" =>
-- carrier
reg_rdat_int(4 downto 0) <= carrier_csr_i.carrier_pcb_rev;
reg_rdat_int(15 downto 5) <= carrier_csr_i.carrier_reserved;
reg_rdat_int(31 downto 16) <= carrier_csr_i.carrier_type;
rd_ack1_int <= rd_int;
when "01" =>
-- stat
reg_rdat_int(0) <= carrier_csr_i.stat_fmc0_pres;
reg_rdat_int(1) <= carrier_csr_i.stat_fmc1_pres;
reg_rdat_int(2) <= carrier_csr_i.stat_sys_pll_lck;
reg_rdat_int(3) <= carrier_csr_i.stat_ddr0_cal_done;
reg_rdat_int(4) <= carrier_csr_i.stat_ddr1_cal_done;
rd_ack1_int <= rd_int;
when "10" =>
-- ctrl
reg_rdat_int(15 downto 0) <= ctrl_fp_leds_man_reg;
rd_ack1_int <= rd_int;
when "11" =>
-- rst
rd_ack1_int <= rd_int;
when others =>
reg_rdat_int <= (others => 'X');
rd_ack1_int <= rd_int;
end case;
end if;
end if;
end process;
-- Process for read requests.
process (wb_i.adr, reg_rdat_int, rd_ack1_int, rd_int) begin
-- By default ack read requests
wb_o.dat <= (others => '0');
case wb_i.adr(3 downto 2) is
when "00" =>
-- carrier
wb_o.dat <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when "01" =>
-- stat
wb_o.dat <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when "10" =>
-- ctrl
wb_o.dat <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when "11" =>
-- rst
wb_o.dat <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when others =>
rd_ack_int <= rd_int;
end case;
end process;
end syn;
hdl/top/svec_ref_design/svec_ref_fmc_adc_100Ms.vhd
View file @ 4f7b5076
......@@ -465,7 +465,7 @@ begin -- architecture arch
------------------------------------------------------------------------------
-- Primary wishbone crossbar
------------------------------------------------------------------------------
cmp_crossbar : entity work.spec_ref_fmc_adc_100m_mmap
cmp_crossbar : entity work.svec_ref_fmc_adc_100m_mmap
port map (
rst_n_i => rst_sys_62m5_n,
clk_i => clk_sys_62m5,
......
software/include/hw/svec_ref_fmc_adc_100Ms_mmap.h
View file @ 4f7b5076
#ifndef __CHEBY__SPEC_REF_FMC_ADC_100M_MMAP__H__
#define __CHEBY__SPEC_REF_FMC_ADC_100M_MMAP__H__
#ifndef __CHEBY__SVEC_REF_FMC_ADC_100M_MMAP__H__
#define __CHEBY__SVEC_REF_FMC_ADC_100M_MMAP__H__
#include "fmc_adc_mezzanine_mmap.h"
#define SPEC_REF_FMC_ADC_100M_MMAP_SIZE 32768
#define SVEC_REF_FMC_ADC_100M_MMAP_SIZE 32768
/* a ROM containing the application metadata */
#define SPEC_REF_FMC_ADC_100M_MMAP_METADATA 0x2000UL
#define SPEC_REF_FMC_ADC_100M_MMAP_METADATA_SIZE 64
#define SVEC_REF_FMC_ADC_100M_MMAP_METADATA 0x2000UL
#define SVEC_REF_FMC_ADC_100M_MMAP_METADATA_SIZE 64
/* FMC ADC Mezzanine slot 1 */
#define SPEC_REF_FMC_ADC_100M_MMAP_FMC1_ADC_MEZZANINE 0x4000UL
#define SPEC_REF_FMC_ADC_100M_MMAP_FMC1_ADC_MEZZANINE_SIZE 8192
#define SVEC_REF_FMC_ADC_100M_MMAP_FMC1_ADC_MEZZANINE 0x4000UL
#define SVEC_REF_FMC_ADC_100M_MMAP_FMC1_ADC_MEZZANINE_SIZE 8192
/* FMC ADC Mezzanine slot 2 */
#define SPEC_REF_FMC_ADC_100M_MMAP_FMC2_ADC_MEZZANINE 0x6000UL
#define SPEC_REF_FMC_ADC_100M_MMAP_FMC2_ADC_MEZZANINE_SIZE 8192
#define SVEC_REF_FMC_ADC_100M_MMAP_FMC2_ADC_MEZZANINE 0x6000UL
#define SVEC_REF_FMC_ADC_100M_MMAP_FMC2_ADC_MEZZANINE_SIZE 8192
struct spec_ref_fmc_adc_100m_mmap {
struct svec_ref_fmc_adc_100m_mmap {
/* padding to: 2048 words */
uint32_t __padding_0[2048];
......@@ -33,4 +33,4 @@ struct spec_ref_fmc_adc_100m_mmap {
struct fmc_adc_mezzanine_mmap fmc2_adc_mezzanine;
};
#endif /* __CHEBY__SPEC_REF_FMC_ADC_100M_MMAP__H__ */
#endif /* __CHEBY__SVEC_REF_FMC_ADC_100M_MMAP__H__ */
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