Merge branch 'adjust-tb' into 'dlamprid-dev'

Adjust tb See merge request dlamprid/fmc-adc-100m14b4cha-gw!1

Merge branch 'adjust-tb' into 'dlamprid-dev'
Adjust tb See merge request dlamprid/fmc-adc-100m14b4cha-gw!1
1ecef9a7 · Dimitris Lampridis · 992cc205 · f2c07d98 · 1ecef9a7 · 1ecef9a7
Commit 1ecef9a7 authored Nov 07, 2018 by Dimitris Lampridis
5 changed files
--- a/hdl/rtl/fmc_adc_100Ms_core_pkg.vhd
+++ b/hdl/rtl/fmc_adc_100Ms_core_pkg.vhd
@@ -52,9 +52,7 @@ package fmc_adc_100Ms_core_pkg is
    generic(
      g_MULTISHOT_RAM_SIZE : natural                        := 2048;
      g_WB_CSR_MODE        : t_wishbone_interface_mode      := PIPELINED;
-      g_WB_CSR_GRANULARITY : t_wishbone_address_granularity := BYTE;
+      g_WB_CSR_GRANULARITY : t_wishbone_address_granularity := BYTE
-      g_WB_DDR_MODE        : t_wishbone_interface_mode      := PIPELINED;
-      g_WB_DDR_GRANULARITY : t_wishbone_address_granularity := BYTE
      );
    port (
      -- Clock, reset

--- a/hdl/rtl/fmc_adc_mezzanine.vhd
+++ b/hdl/rtl/fmc_adc_mezzanine.vhd
@@ -112,28 +112,6 @@ end fmc_adc_mezzanine;
 architecture rtl of fmc_adc_mezzanine is
-  ------------------------------------------------------------------------------
-  -- Components declaration
-  ------------------------------------------------------------------------------
-  component fmc_adc_eic
-    port (
-      rst_n_i       : in  std_logic;
-      clk_sys_i     : in  std_logic;
-      wb_adr_i      : in  std_logic_vector(1 downto 0);
-      wb_dat_i      : in  std_logic_vector(31 downto 0);
-      wb_dat_o      : out std_logic_vector(31 downto 0);
-      wb_cyc_i      : in  std_logic;
-      wb_sel_i      : in  std_logic_vector(3 downto 0);
-      wb_stb_i      : in  std_logic;
-      wb_we_i       : in  std_logic;
-      wb_ack_o      : out std_logic;
-      wb_stall_o    : out std_logic;
-      wb_int_o      : out std_logic;
-      irq_trig_i    : in  std_logic;
-      irq_acq_end_i : in  std_logic
-      );
-  end component fmc_adc_eic;
  ------------------------------------------------------------------------------
  -- SDB crossbar constants declaration
  ------------------------------------------------------------------------------
@@ -496,7 +474,7 @@ begin
  ------------------------------------------------------------------------------
  -- FMC0 interrupt controller
  ------------------------------------------------------------------------------
-  cmp_fmc0_eic : fmc_adc_eic
+  cmp_fmc0_eic : entity work.fmc_adc_eic
    port map(
      rst_n_i       => sys_rst_n_i,
      clk_sys_i     => sys_clk_i,

--- a/hdl/rtl/timetag_core/timetag_core.vhd
+++ b/hdl/rtl/timetag_core/timetag_core.vhd
@@ -110,6 +110,9 @@ architecture rtl of timetag_core is
  signal acq_stop_tag  : t_timetag;
  signal acq_end_tag   : t_timetag;
+  signal time_trig     : std_logic;
+  signal time_trig_d   : std_logic;
  signal local_pps : std_logic;
  signal wr_enabled : std_logic := '0';
@@ -209,10 +212,21 @@ begin
  ------------------------------------------------------------------------------
  -- Time trigger signal generation (stretched to two 125MHz cycles)
  ------------------------------------------------------------------------------
-  time_trig_o <= '1' when ((time_trigger = current_time) or
-                           ((time_trigger.seconds = current_time.seconds) and
+  time_trig <= '1' when (time_trigger = current_time) else '0';
-                            (unsigned(time_trigger.coarse) + 1 = unsigned(current_time.coarse))))
-                 else '0';
+  process (clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if rst_n_i = '0' then
+        time_trig_d <= '0';
+      else
+        time_trig_d <= time_trig;
+      end if;
+    end if;
+  end process;
+  time_trig_o <= time_trig or time_trig_d;
  ------------------------------------------------------------------------------
  -- Last trigger event time-tag

--- a/hdl/testbench/fmc_adc_mezzanine/Manifest.py
+++ b/hdl/testbench/fmc_adc_mezzanine/Manifest.py
@@ -12,6 +12,7 @@ fetchto = "../../ip_cores"
 include_dirs = [
    "../include",
    fetchto + "/general-cores/sim/",
+    fetchto + "/general-cores/modules/wishbone/wb_spi/"
 ]
 files = [

--- a/hdl/testbench/fmc_adc_mezzanine/main.sv
+++ b/hdl/testbench/fmc_adc_mezzanine/main.sv
@@ -21,8 +21,10 @@ module main;
   reg[3:0] adc0_dat_even = 4'h0;
   reg signed [13:0] adc0_data = 0;
+   // 400Mhz
   always #1.25ns adc0_dco <= ~adc0_dco;
+   // 125Mhz
   always #4ns clk_sys <= ~clk_sys;
   initial begin
@@ -32,30 +34,21 @@ module main;
   IVHDWishboneMaster Host ( clk_sys, rst_n );
+   wire t_wishbone_slave_data64_out dummy_wb64_out =
+        '{ack: 1'b1, err: 1'b0, rty: 1'b0, stall: 1'b0, dat: 64'bx};
   fmc_adc_mezzanine
     #(
       .g_multishot_ram_size(2048)
       ) DUT (
 	      .sys_clk_i           (clk_sys),
 	      .sys_rst_n_i         (rst_n),
-	      .wb_csr_adr_i        (Host.out.adr),
+	      .wb_csr_slave_i      (Host.out),
-	      .wb_csr_dat_i        (Host.out.dat),
+	      .wb_csr_slave_o      (Host.in),
-	      .wb_csr_dat_o        (Host.in.dat),
-	      .wb_csr_cyc_i        (Host.out.cyc),
-	      .wb_csr_sel_i        (Host.out.sel),
-	      .wb_csr_stb_i        (Host.out.stb),
-	      .wb_csr_we_i         (Host.out.we),
-	      .wb_csr_ack_o        (Host.in.ack),
-	      .wb_csr_stall_o      (Host.in.stall),
 	      .wb_ddr_clk_i        (clk_sys),
-	      .wb_ddr_adr_o        (),
+              .wb_ddr_rst_n_i      (rst_n),
-	      .wb_ddr_dat_o        (),
+	      .wb_ddr_master_i     (dummy_wb64_out),
-	      .wb_ddr_sel_o        (),
+              .wb_ddr_master_o     (),
-	      .wb_ddr_stb_o        (),
-	      .wb_ddr_we_o         (),
-	      .wb_ddr_cyc_o        (),
-	      .wb_ddr_ack_i        (1'b1),
-	      .wb_ddr_stall_i      (1'b0),
 	      .ddr_wr_fifo_empty_i (),
 	      .trig_irq_o          (),
 	      .acq_end_irq_o       (),
@@ -111,6 +104,7 @@ module main;
 	end
     end
+   //  Generate a triangular waveform on all channels.
   always@(posedge adc0_fr)
     begin
 	if ((adc0_data > 400) || (adc0_data < -400)) begin