Project description
FmcAdc100k16b8cha is a 8 channel 100kSPS 16 bit ADC card in FMC (FPGA Mezzanine Card) standard. Input voltage range is fixed to +/-10V. Input impedance is 1MOhm.
Parameter | Value |
max. sample rate | 200 kS/s max. |
bits/sample | 16 bit |
input voltage range | /-10 V,/-5 V software selectable |
channels | 13 - custom made cable, 11 - standard camera link cable |
connectors | Connector Mini D Ribbon (MDR), CAMERA LINK compatible |
analog bandwidth | 22 kHz ( /-10 V), 14 kHz (/-5 V) |
antialiasing filter | 2-pole, included |
input impedance | 1MOhm |
FMC to carrier interface | FMC low pin count connector |
ADC interface | standard (/RD, /WR, parallel data bus |
Clock [link](https://www.ohwr.org/project/fmc-adc-100k16b8cha/blob/master | )internal VCO - for synchronization ability |
Trigger | External and internal with threshold and slope |
Timebase | 200 kS/s to 100 S/s in 1, 2, 5 steps |
Delay | From - Timebase to 2^32 samples |
Time stamps | for trigger, resettable by software |
Coupling | DC only |
Block diagram
Project documents
FmcAdc100k16b8cha schematics - PDF file:
https://www.ohwr.org/project/fmc-adc-100k16b8cha/uploads/098981866f59b2d87ae4d6d5b56556cd/FmcAdc16b100k8cha.pdf
FmcAdc100k16b8cha PCB - PDF file:
https://www.ohwr.org/project/fmc-adc-100k16b8cha/uploads/26e4ba2e83894ddfe446c27e21301cc4/PCB.pdf
Short description of the
schematic:
https://www.ohwr.org/project/fmc-adc-100k16b8cha/uploads/3a606da49dfb68cff5856a78438dcca9/FmcAdc100k16b13cha_description.pdf
Comparison of three ADCs that could be potentially used in the project -
PDF
file:
https://www.ohwr.org/project/fmc-adc-100k16b8cha/uploads/923ad2dbacc71aff723cb56429b62fb2/FmcAdc_8_channel_-_ADC_comparison.pdf
Connector choice (also used in the digital I/O FMC
project)
https://www.ohwr.org/project/fmc-dio-16chttla/wikis/Connector_choice
Status
Date | Event |
29-03-2010 | ADC choice made. First draft of the design idea. |
30-03-2010 | Price estimation and widened feature list added. Waiting for the Altium Designer ADC symbol. |
12-07-2010 | Restart of design work. |
20-09-2010 | The PCB is now ready. Waiting for VHDL to be developed. |
Maciej Fimiarz, Erik van der Bij - 15 July 2010