Project description
FmcAdc100k16b8cha is a 8 channel 100kSPS 16 bit ADC card in FMC (FPGA Mezzanine Card) standard. Input voltage range is fixed to +/-10V. Input impedance is 1MOhm.
Parameter | Value |
max. sample rate | 100 kS/s |
bits/sample | 16 bit |
channels | 8 |
connectors | Connector Mini D Ribbon (MDR) 36 Female |
analog bandwidth | 25 kHz |
antialiasing filter | 2-pole, included |
input impedance | 1MOhm |
input voltage range | +/-10V, more ranges are welcome if could be done easily (for ex. by changing ADC settings) |
FMC to carrier interface | FMC low pin count connector |
ADC interface | serial (SPI compatible) or parallel CMOS |
Clock [link](https://www.ohwr.org/project/fmc-adc-100k16b8cha/blob/master | )internal only |
Trigger | External and internal with threshold and slope |
Timebase | 100 kS/s to 100 S/s in 1, 2, 5 steps |
Delay | From -Timebase to 2^32 samples |
Time stamps | for trigger, resettable by software |
Coupling | DC only |
Block diagram
Project documents
FmcAdc100k16b8cha schematics
https://www.ohwr.org/project/fmc-adc-100k16b8cha/uploads/6c7304303a2e2c8cf0a5da8e7af0cab3/schematics.pdf
FmcAdc100k16b8cha features
list:
https://www.ohwr.org/120
FmcAdc100k16b8cha price
estimation:
https://www.ohwr.org/118
Comparison of three ADCs that could be potentially used in the project -
PDF
file:
https://www.ohwr.org/project/fmc-adc-100k16b8cha/uploads/923ad2dbacc71aff723cb56429b62fb2/FmcAdc_8_channel_-_ADC_comparison.pdf
Connector choice (also used in the digital I/O FMC
project)
https://www.ohwr.org/project/fmc-dio-16chttla/wikis/Connector_choice
Status
Date | Event |
29-03-2010 | ADC choice made. First draft of the design idea. |
30-03-2010 | Price estimation and widened feature list added. Waiting for the Altium Designer ADC symbol. |
12-07-2010 | Restart of design work. |
Maciej Firmiarz, Erik van der Bij - 15 July 2010