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FMC DEL 1ns 4cha - Software
Commit 16a85cbb authored by Federico Vaga's avatar Federico Vaga
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drv: update HW header file 

Signed-off-by: Federico Vaga's avatarFederico Vaga <federico.vaga@cern.ch>
parent 3456b120
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Showing with 22 additions and 21 deletions
kernel/hw/fd_main_regs.h
View file @ 16a85cbb
/*
Register definitions for slave core: Fine Delay Main WB Slave
* File : /tmp/head.h
* Author : auto-generated by wbgen2 from hdl/rtl/fd_main_wishbone_slave.wb
* Created : Wed Sep 11 17:19:19 2019
* File : fd_main_regs.h
* Author : auto-generated by wbgen2 from fd_main_wishbone_slave.wb
* Created : Fri Apr 24 22:09:52 2020
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE hdl/rtl/fd_main_wishbone_slave.wb
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_main_wishbone_slave.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
......@@ -134,15 +134,6 @@
/* definitions for field: IDELAY CE (pulse) in reg: Host-driven TDC Control/Status */
#define FD_TDCSR_IDELAY_CE WBGEN2_GEN_MASK(8, 1)
/* definitions for field: IDELAY RST (GPIO) in reg: Host-driven TDC Control/Status */
#define FD_TDCSR_IDELAY_RST WBGEN2_GEN_MASK(9, 1)
/* definitions for field: IDELAY CAL (GPIO) in reg: Host-driven TDC Control/Status */
#define FD_TDCSR_IDELAY_CAL WBGEN2_GEN_MASK(10, 1)
/* definitions for field: IDELAY CAL (GPIO) in reg: Host-driven TDC Control/Status */
#define FD_TDCSR_IDELAY_INC WBGEN2_GEN_MASK(11, 1)
/* definitions for register: Calibration register */
/* definitions for field: Generate calibration pulses (type 1 calibration) in reg: Calibration register */
......@@ -366,6 +357,14 @@
#define FD_FMC_SLOT_ID_SLOT_ID_W(value) WBGEN2_GEN_WRITE(value, 0, 4)
#define FD_FMC_SLOT_ID_SLOT_ID_R(reg) WBGEN2_GEN_READ(reg, 0, 4)
/* definitions for register: I/O Delay Adjust Register */
/* definitions for field: Number of delay line taps. in reg: I/O Delay Adjust Register */
#define FD_IODELAY_ADJ_N_TAPS_MASK WBGEN2_GEN_MASK(0, 6)
#define FD_IODELAY_ADJ_N_TAPS_SHIFT 0
#define FD_IODELAY_ADJ_N_TAPS_W(value) WBGEN2_GEN_WRITE(value, 0, 6)
#define FD_IODELAY_ADJ_N_TAPS_R(reg) WBGEN2_GEN_READ(reg, 0, 6)
/* definitions for register: Interrupt disable register */
/* definitions for field: Timestamp Buffer interrupt. in reg: Interrupt disable register */
......@@ -473,12 +472,14 @@
#define FD_REG_TSBR_ADVANCE 0x00000078
/* [0x7c]: REG FMC Slot ID Register */
#define FD_REG_FMC_SLOT_ID 0x0000007c
/* [0x80]: REG Interrupt disable register */
#define FD_REG_EIC_IDR 0x00000080
/* [0x84]: REG Interrupt enable register */
#define FD_REG_EIC_IER 0x00000084
/* [0x88]: REG Interrupt mask register */
#define FD_REG_EIC_IMR 0x00000088
/* [0x8c]: REG Interrupt status register */
#define FD_REG_EIC_ISR 0x0000008c
/* [0x80]: REG I/O Delay Adjust Register */
#define FD_REG_IODELAY_ADJ 0x00000080
/* [0xa0]: REG Interrupt disable register */
#define FD_REG_EIC_IDR 0x000000a0
/* [0xa4]: REG Interrupt enable register */
#define FD_REG_EIC_IER 0x000000a4
/* [0xa8]: REG Interrupt mask register */
#define FD_REG_EIC_IMR 0x000000a8
/* [0xac]: REG Interrupt status register */
#define FD_REG_EIC_ISR 0x000000ac
#endif
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