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FPGA and ARM SoC FMC Carrier FASEC
Commit e3139120 authored by Pieter Van Trappen's avatar Pieter Van Trappen
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submodule cores updated for fasec_hwtest v3.2.2, outputs generated

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.Xil/Vivado-3878-lapte24154/coregen/clock_temp/clock_temp.xci 0 → 100644
View file @ e3139120
<?xml version="1.0" encoding="UTF-8"?>
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>xci</spirit:library>
<spirit:name>unknown</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>clock_temp</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="signal.param" spirit:name="clock" spirit:version="1.0"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ASSOCIATED_ASYNC_RESET">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ASSOCIATED_BUSIF">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ASSOCIATED_CLKEN">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ASSOCIATED_MMCM_LOCK">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ASSOCIATED_RESET">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_DOMAIN">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">clock_temp</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PortWidth">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z030</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg676</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator_BusInterface</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2016.2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
</spirit:configurableElementValues>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>
.Xil/Vivado-3878-lapte24154/coregen/clock_temp/clock_temp.xml 0 → 100644
View file @ e3139120
<?xml version="1.0" encoding="UTF-8"?>
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>customized_ip</spirit:library>
<spirit:name>clock_temp</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:model>
<spirit:ports>
<spirit:port>
<spirit:name>const</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">0</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
</spirit:ports>
</spirit:model>
<spirit:description>intf_clock_v1_0</spirit:description>
<spirit:parameters>
<spirit:parameter>
<spirit:name>PortWidth</spirit:name>
<spirit:displayName>Portwidth</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PortWidth" spirit:order="1100">0</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_CLKEN</spirit:name>
<spirit:displayName>Associated Clken</spirit:displayName>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.ASSOCIATED_CLKEN" spirit:order="1200">0</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_RESET</spirit:name>
<spirit:displayName>Associated Reset</spirit:displayName>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.ASSOCIATED_RESET" spirit:order="1300">0</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_ASYNC_RESET</spirit:name>
<spirit:displayName>Associated Async Reset</spirit:displayName>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.ASSOCIATED_ASYNC_RESET" spirit:order="1400">0</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_MMCM_LOCK</spirit:name>
<spirit:displayName>Associated MMCM Lock</spirit:displayName>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.ASSOCIATED_MMCM_LOCK" spirit:order="1500">0</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
<spirit:displayName>Associated Busif</spirit:displayName>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.ASSOCIATED_BUSIF" spirit:order="1600">0</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:displayName>Clk Domain</spirit:displayName>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_DOMAIN" spirit:order="1700">0</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>PHASE</spirit:name>
<spirit:displayName>Phase</spirit:displayName>
<spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PHASE" spirit:order="1800">0</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:displayName>Frequency</spirit:displayName>
<spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.FREQ_HZ" spirit:order="1900">100000000</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>Component_Name</spirit:name>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">clock_temp</spirit:value>
</spirit:parameter>
</spirit:parameters>
<spirit:vendorExtensions>
<xilinx:coreExtensions>
<xilinx:displayName>intf_clock_v1_0</xilinx:displayName>
<xilinx:coreRevision>1</xilinx:coreRevision>
<xilinx:tags>
<xilinx:tag xilinx:name="nopcore"/>
</xilinx:tags>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2013.3.0</xilinx:xilinxVersion>
</xilinx:packagingInfo>
</spirit:vendorExtensions>
</spirit:component>
.Xil/Vivado-3878-lapte24154/coregen/interrupt_temp/interrupt_temp.xci 0 → 100644
View file @ e3139120
<?xml version="1.0" encoding="UTF-8"?>
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>xci</spirit:library>
<spirit:name>unknown</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>interrupt_temp</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="signal.param" spirit:name="interrupt" spirit:version="1.0"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">interrupt_temp</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PortWidth">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SENSITIVITY">LEVEL_HIGH</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z030</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg676</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator_BusInterface</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2016.2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
</spirit:configurableElementValues>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>
.Xil/Vivado-3878-lapte24154/coregen/interrupt_temp/interrupt_temp.xml 0 → 100644
View file @ e3139120
<?xml version="1.0" encoding="UTF-8"?>
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>customized_ip</spirit:library>
<spirit:name>interrupt_temp</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:model>
<spirit:ports>
<spirit:port>
<spirit:name>dummy</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;PARAM_VALUE.PortWidth&apos;-1)))">0</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
</spirit:ports>
</spirit:model>
<spirit:description>Parameter Definition for Interrupt</spirit:description>
<spirit:parameters>
<spirit:parameter>
<spirit:name>SENSITIVITY</spirit:name>
<spirit:displayName>Interrupt Sensivity</spirit:displayName>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.SENSITIVITY" spirit:order="100">LEVEL_HIGH</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>PortWidth</spirit:name>
<spirit:displayName>Port Width</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PortWidth" spirit:order="200">1</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>Component_Name</spirit:name>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">interrupt_temp</spirit:value>
</spirit:parameter>
</spirit:parameters>
<spirit:vendorExtensions>
<xilinx:coreExtensions>
<xilinx:displayName>Intf_Interrupt</xilinx:displayName>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2013.3.0</xilinx:xilinxVersion>
</xilinx:packagingInfo>
</spirit:vendorExtensions>
</spirit:component>
.Xil/Vivado-3878-lapte24154/coregen/reset_temp/reset_temp.xci 0 → 100644
View file @ e3139120
<?xml version="1.0" encoding="UTF-8"?>
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>xci</spirit:library>
<spirit:name>unknown</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>reset_temp</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="signal.param" spirit:name="reset" spirit:version="1.0"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">reset_temp</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PortWidth">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TYPE">PERIPHERAL</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z030</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg676</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator_BusInterface</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2016.2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
</spirit:configurableElementValues>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>
.Xil/Vivado-3878-lapte24154/coregen/reset_temp/reset_temp.xml 0 → 100644
View file @ e3139120
<?xml version="1.0" encoding="UTF-8"?>
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>customized_ip</spirit:library>
<spirit:name>reset_temp</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:model>
<spirit:ports>
<spirit:port>
<spirit:name>const</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">0</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
</spirit:ports>
</spirit:model>
<spirit:choices>
<spirit:choice>
<spirit:name>choice_list_6eff49bd</spirit:name>
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
</spirit:choice>
</spirit:choices>
<spirit:description>intf_reset_v1_0</spirit:description>
<spirit:parameters>
<spirit:parameter>
<spirit:name>PortWidth</spirit:name>
<spirit:displayName>Portwidth</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PortWidth" spirit:order="1500">1</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>POLARITY</spirit:name>
<spirit:displayName>Polarity</spirit:displayName>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.POLARITY" spirit:choiceRef="choice_list_6eff49bd" spirit:order="1300" spirit:configGroups="0 UnGrouped radioGroup">ACTIVE_LOW</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>Component_Name</spirit:name>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">reset_temp</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>TYPE</spirit:name>
<spirit:displayName>Type</spirit:displayName>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.TYPE" spirit:order="1200">PERIPHERAL</spirit:value>
</spirit:parameter>
</spirit:parameters>
<spirit:vendorExtensions>
<xilinx:coreExtensions>
<xilinx:displayName>intf_reset_v1_0</xilinx:displayName>
<xilinx:coreRevision>1</xilinx:coreRevision>
<xilinx:tags>
<xilinx:tag xilinx:name="nopcore"/>
</xilinx:tags>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2014.1.0</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="8c78762f"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="afa03a67"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="d39624b6"/>
</xilinx:packagingInfo>
</spirit:vendorExtensions>
</spirit:component>
FASEC_prototype.ip_user_files/bd/system_design/hdl/system_design.vhd
View file @ e3139120
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
--Date : Thu May 11 16:53:06 2017
--Date : Thu May 11 18:13:27 2017
--Host : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
--Command : generate_target system_design.bd
--Design : system_design
......
FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd
View file @ e3139120
......@@ -46,8 +46,8 @@
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: user.org:user:fasec_hwtest:3.2.1
-- IP Revision: 29
-- IP VLNV: user.org:user:fasec_hwtest:3.2.2
-- IP Revision: 30
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
......
FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd → FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd
View file @ e3139120
......@@ -65,9 +65,9 @@ entity general_fmc is
FMC_CLK0C2M_P_o : out std_logic;
FMC_CLK0C2M_N_o : out std_logic;
-- FMC general purpose
FMC_GP0_i : in std_logic;
FMC_GP1_i : in std_logic;
FMC_GP2_i : in std_logic;
FMC_GP0_i : in std_logic;
FMC_GP1_i : in std_logic;
FMC_GP2_i : in std_logic;
FMC_GP3_b : inout std_logic;
-- generic registers for passing data to top module
-- rw data, modified by master
......@@ -93,12 +93,16 @@ architecture rtl of general_fmc is
constant c_COUNTERWIDTH : positive := 24;
constant c_LEDCOUNTERWIDTH : positive := 32;
-- memory mapping EDA-03287:
constant c_ADDR_COMPIN : positive := 16#00#;
constant c_ADDR_COMPEXIN : positive := 16#04#;
constant c_ADDR_OUTEXIN : positive := 16#05#;
-- 0x00 : General Purpose
-- 0x00 ro : bit19-0 comparator input status
-- 0x01 ro : bit3-0 output feedback status
-- 0x02 rw : bit7-0 output request
-- 0x03 rw : DAC control (see dac7716_spi.vhd)
-- 0x04 ro : bit19-0 extended input status for LEDs
-- 0x05 ro : bit7-0 extended output status for LEDs
-- 0x08 rw : 20x channel write request
-- 0x1C ro : 20x channel read values
-- 0x30 ro : 20x pulse length counter (assserted pulse)
......@@ -112,7 +116,7 @@ architecture rtl of general_fmc is
type t_cmplengths is array (0 to c_COMP-1) of std_logic_vector(c_COUNTERWIDTH-1 downto 0);
signal s_cmp_lengths : t_cmplengths;
signal s_diffouts_o : std_logic_vector(c_DOUTS-1 downto 0);
signal s_outleds : std_logic_vector(c_DOUTS-1 downto 0);
signal s_outleds : std_logic_vector(c_DOUTS-1 downto 0);
signal s_outsfeedbak_i : std_logic_vector(c_OUTFBD-1 downto 0);
signal s_spi_sclk : std_logic;
signal s_spi_mosi : std_logic;
......@@ -286,10 +290,10 @@ begin
end generate gen_clkouts;
p_fmc_03287_io : process(clk_i)
variable v_cmp : std_logic_vector(c_COMP-1 downto 0);
variable v_cmpled : std_logic_vector(c_COMP-1 downto 0);
variable v_dout : std_logic_vector(c_DOUTS-1 downto 0);
variable v_fbd : std_logic_vector(c_OUTFBD-1 downto 0);
variable v_cmp : std_logic_vector(c_COMP-1 downto 0);
variable v_cmpled : std_logic_vector(c_COMP-1 downto 0);
variable v_dout : std_logic_vector(c_DOUTS-1 downto 0);
variable v_fbd : std_logic_vector(c_OUTFBD-1 downto 0);
variable v_outleds : std_logic_vector(c_DOUTS-1 downto 0);
begin
if g_FMC = "EDA-03287" and rising_edge(clk_i) then
......@@ -311,15 +315,16 @@ begin
intr_led_o <= '0';
end if;
-- clocking in data for above interrupt generation
v_cmpled := s_compleds(c_COMP-1 downto 0);
v_cmp := s_cmp_pulse(c_COMP-1 downto 0);
v_outleds := s_outleds(c_DOUTS-1 downto 0);
-- leds combination from status and extended pulse
v_cmp := s_cmp_pulse(c_COMP-1 downto 0);
v_cmpled := s_compleds(c_COMP-1 downto 0) or s_cmp_pulse(c_COMP-1 downto 0);
v_outleds := s_outleds(c_DOUTS-1 downto 0) or v_dout(c_DOUTS-1 downto 0);
end if;
end process p_fmc_03287_io;
-- no additional clocking of comparators & LEDs
data_o(0) <= resize(unsigned(s_cmp_pulse), data_o(0)'length);
data_o(4) <= resize(unsigned(s_compleds), data_o(0)'length);
data_o(c_ADDR_COMPIN) <= resize(unsigned(s_cmp_pulse), data_o(0)'length);
data_o(c_ADDR_COMPEXIN) <= resize(unsigned(s_compleds), data_o(0)'length);
data_o(c_ADDR_OUTEXIN) <= resize(unsigned(s_outleds), data_o(0)'length);
--=============================================================================
-- EDA-02327: FMC user lines - clock in for AXI register read by Zynq PS
--=============================================================================
......
FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/README.txt
View file @ e3139120
......@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Thu May 11 16:53:13 CEST 2017
# Generated by export_simulation on Thu May 11 18:13:34 CEST 2017
#
################################################################################
......
FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/compile.do
View file @ e3139120
......@@ -91,22 +91,22 @@ vlog -work xil_defaultlib -v2k5 "+incdir+../../../ipstatic/axi_infrastructure_v1
"../../../bd/system_design/ip/system_design_processing_system7_0_0/sim/system_design_processing_system7_0_0.v" \
vcom -work hdl_lib -93 \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/main_pkg.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/ip_cores/hdl_lib/modules/main_pkg.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd" \
vcom -work xil_defaultlib -93 \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" \
vcom -work hdl_lib -93 \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/ip_cores/hdl_lib/modules/general/clockDivider.vhd" \
vcom -work xil_defaultlib -93 \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" \
"../../../bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd" \
vcom -work lib_cdc_v1_0_2 -93 \
......
FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/system_design.sh
View file @ e3139120
......@@ -8,7 +8,7 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Thu May 11 16:53:13 CEST 2017
# Generated by Vivado on Thu May 11 18:13:34 CEST 2017
# IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016
#
# usage: system_design.sh [-help]
......
FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/README.txt
View file @ e3139120
......@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Thu May 11 16:53:13 CEST 2017
# Generated by export_simulation on Thu May 11 18:13:34 CEST 2017
#
################################################################################
......
FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/run.f
View file @ e3139120
......@@ -40,22 +40,22 @@
"../../../bd/system_design/ip/system_design_processing_system7_0_0/sim/system_design_processing_system7_0_0.v" \
-endlib
-makelib ies/hdl_lib \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/main_pkg.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/ip_cores/hdl_lib/modules/main_pkg.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd" \
-endlib
-makelib ies/xil_defaultlib \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" \
-endlib
-makelib ies/hdl_lib \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/ip_cores/hdl_lib/modules/general/clockDivider.vhd" \
-endlib
-makelib ies/xil_defaultlib \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" \
"../../../bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd" \
-endlib
-makelib ies/lib_cdc_v1_0_2 \
......
FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/system_design.sh
View file @ e3139120
......@@ -8,7 +8,7 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Thu May 11 16:53:13 CEST 2017
# Generated by Vivado on Thu May 11 18:13:34 CEST 2017
# IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016
#
# usage: system_design.sh [-help]
......
FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/README.txt
View file @ e3139120
......@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Thu May 11 16:53:13 CEST 2017
# Generated by export_simulation on Thu May 11 18:13:34 CEST 2017
#
################################################################################
......
FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/compile.do
View file @ e3139120
......@@ -91,22 +91,22 @@ vlog -work xil_defaultlib -64 -incr "+incdir+../../../ipstatic/axi_infrastructur
"../../../bd/system_design/ip/system_design_processing_system7_0_0/sim/system_design_processing_system7_0_0.v" \
vcom -work hdl_lib -64 -93 \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/main_pkg.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/ip_cores/hdl_lib/modules/main_pkg.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd" \
vcom -work xil_defaultlib -64 -93 \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" \
vcom -work hdl_lib -64 -93 \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/ip_cores/hdl_lib/modules/general/clockDivider.vhd" \
vcom -work xil_defaultlib -64 -93 \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" \
"../../../bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd" \
vcom -work lib_cdc_v1_0_2 -64 -93 \
......
FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/system_design.sh
View file @ e3139120
......@@ -8,7 +8,7 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Thu May 11 16:53:13 CEST 2017
# Generated by Vivado on Thu May 11 18:13:34 CEST 2017
# IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016
#
# usage: system_design.sh [-help]
......
FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/README.txt
View file @ e3139120
......@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Thu May 11 16:53:13 CEST 2017
# Generated by export_simulation on Thu May 11 18:13:34 CEST 2017
#
################################################################################
......
FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/compile.do
View file @ e3139120
......@@ -91,22 +91,22 @@ vlog -work xil_defaultlib -64 "+incdir+../../../ipstatic/axi_infrastructure_v1_1
"../../../bd/system_design/ip/system_design_processing_system7_0_0/sim/system_design_processing_system7_0_0.v" \
vcom -work hdl_lib -64 \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/main_pkg.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/ip_cores/hdl_lib/modules/main_pkg.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd" \
vcom -work xil_defaultlib -64 \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" \
vcom -work hdl_lib -64 \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/ip_cores/hdl_lib/modules/general/clockDivider.vhd" \
vcom -work xil_defaultlib -64 \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" \
"../../../bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd" \
vcom -work lib_cdc_v1_0_2 -64 \
......
FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/system_design.sh
View file @ e3139120
......@@ -8,7 +8,7 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Thu May 11 16:53:13 CEST 2017
# Generated by Vivado on Thu May 11 18:13:34 CEST 2017
# IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016
#
# usage: system_design.sh [-help]
......
FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/README.txt
View file @ e3139120
......@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Thu May 11 16:53:13 CEST 2017
# Generated by export_simulation on Thu May 11 18:13:34 CEST 2017
#
################################################################################
......
FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/compile.do
View file @ e3139120
......@@ -91,22 +91,22 @@ vlog -work xil_defaultlib -v2k5 "+incdir+../../../ipstatic/axi_infrastructure_v1
"../../../bd/system_design/ip/system_design_processing_system7_0_0/sim/system_design_processing_system7_0_0.v" \
vcom -work hdl_lib -93 \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/main_pkg.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/ip_cores/hdl_lib/modules/main_pkg.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd" \
vcom -work xil_defaultlib -93 \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" \
vcom -work hdl_lib -93 \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/ip_cores/hdl_lib/modules/general/clockDivider.vhd" \
vcom -work xil_defaultlib -93 \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" \
"../../../bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd" \
vcom -work lib_cdc_v1_0_2 -93 \
......
FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/system_design.sh
View file @ e3139120
......@@ -8,7 +8,7 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Thu May 11 16:53:13 CEST 2017
# Generated by Vivado on Thu May 11 18:13:34 CEST 2017
# IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016
#
# usage: system_design.sh [-help]
......
FASEC_prototype.ip_user_files/sim_scripts/system_design/vcs/README.txt
View file @ e3139120
......@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Thu May 11 16:53:13 CEST 2017
# Generated by export_simulation on Thu May 11 18:13:34 CEST 2017
#
################################################################################
......
FASEC_prototype.ip_user_files/sim_scripts/system_design/vcs/system_design.sh
View file @ e3139120
......@@ -8,7 +8,7 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Thu May 11 16:53:13 CEST 2017
# Generated by Vivado on Thu May 11 18:13:34 CEST 2017
# IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016
#
# usage: system_design.sh [-help]
......@@ -113,25 +113,25 @@ compile()
2>&1 | tee -a vlogan.log
vhdlan -work hdl_lib $vhdlan_opts \
"$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" \
"$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" \
"$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" \
"$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/main_pkg.vhd" \
"$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd" \
"$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" \
"$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" \
"$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" \
"$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/ip_cores/hdl_lib/modules/main_pkg.vhd" \
"$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd" \
2>&1 | tee -a vhdlan.log
vhdlan -work xil_defaultlib $vhdlan_opts \
"$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" \
"$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" \
2>&1 | tee -a vhdlan.log
vhdlan -work hdl_lib $vhdlan_opts \
"$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" \
"$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd" \
"$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" \
"$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/ip_cores/hdl_lib/modules/general/clockDivider.vhd" \
2>&1 | tee -a vhdlan.log
vhdlan -work xil_defaultlib $vhdlan_opts \
"$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" \
"$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" \
"$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" \
"$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" \
"$ref_dir/../../../bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd" \
2>&1 | tee -a vhdlan.log
......
FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/README.txt
View file @ e3139120
......@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Thu May 11 16:53:13 CEST 2017
# Generated by export_simulation on Thu May 11 18:13:34 CEST 2017
#
################################################################################
......
FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/system_design.sh
View file @ e3139120
......@@ -8,7 +8,7 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Thu May 11 16:53:13 CEST 2017
# Generated by Vivado on Thu May 11 18:13:34 CEST 2017
# IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016
#
# usage: system_design.sh [-help]
......
FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/vhdl.prj
View file @ e3139120
vhdl xpm "/local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_VCOMP.vhd"
vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd"
vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd"
vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd"
vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/main_pkg.vhd"
vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd"
vhdl xil_defaultlib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd"
vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd"
vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd"
vhdl xil_defaultlib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd"
vhdl xil_defaultlib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd"
vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd"
vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd"
vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/ip_cores/hdl_lib/modules/general/counterUpDown.vhd"
vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/ip_cores/hdl_lib/modules/main_pkg.vhd"
vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd"
vhdl xil_defaultlib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd"
vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd"
vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/ip_cores/hdl_lib/modules/general/clockDivider.vhd"
vhdl xil_defaultlib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd"
vhdl xil_defaultlib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd"
vhdl xil_defaultlib "../../../bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd"
vhdl lib_cdc_v1_0_2 "../../../ipstatic/lib_cdc_v1_0/hdl/src/vhdl/cdc_sync.vhd"
vhdl proc_sys_reset_v5_0_9 "../../../ipstatic/proc_sys_reset_v5_0/hdl/src/vhdl/upcnt_n.vhd"
......
FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design.vhd
View file @ e3139120
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
--Date : Thu May 11 16:53:06 2017
--Date : Thu May 11 18:13:27 2017
--Host : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
--Command : generate_target system_design.bd
--Design : system_design
......
FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design_wrapper.vhd
View file @ e3139120
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
--Date : Thu May 11 16:53:07 2017
--Date : Thu May 11 18:13:27 2017
--Host : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
--Command : generate_target system_design_wrapper.bd
--Design : system_design_wrapper
......
FASEC_prototype.srcs/sources_1/bd/system_design/hw_handoff/system_design.hwh
View file @ e3139120
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Thu May 11 16:53:08 2017" VIVADOVERSION="2016.2">
<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Thu May 11 18:13:28 2017" VIVADOVERSION="2016.2">
<SYSTEMINFO ARCH="zynq" DEVICE="7z030" NAME="system_design" PACKAGE="ffg676" SPEEDGRADE="-2"/>
......@@ -3685,7 +3685,7 @@
</BUSINTERFACE>
</BUSINTERFACES>
</MODULE>
<MODULE FULLNAME="/fasec_hwtest_0" HWVERSION="3.2.1" INSTANCE="fasec_hwtest_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="fasec_hwtest" VLNV="user.org:user:fasec_hwtest:3.2.1">
<MODULE FULLNAME="/fasec_hwtest_0" HWVERSION="3.2.2" INSTANCE="fasec_hwtest_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="fasec_hwtest" VLNV="user.org:user:fasec_hwtest:3.2.2">
<DOCUMENTS/>
<ADDRESSBLOCKS>
<ADDRESSBLOCK ACCESS="" INTERFACE="S00_AXI" NAME="S00_AXI_reg" RANGE="4096" USAGE=""/>
......
FASEC_prototype.srcs/sources_1/bd/system_design/hw_handoff/system_design_bd.tcl
View file @ e3139120
......@@ -247,7 +247,7 @@ CONFIG.C_S_AXI_ACLK_FREQ_HZ.VALUE_SRC {DEFAULT} \
set axi_wb_i2c_master_2 [ create_bd_cell -type ip -vlnv cern.ch:ip:axi_wb_i2c_master:3.1.1 axi_wb_i2c_master_2 ]
# Create instance: fasec_hwtest_0, and set properties
set fasec_hwtest_0 [ create_bd_cell -type ip -vlnv user.org:user:fasec_hwtest:3.2.1 fasec_hwtest_0 ]
set fasec_hwtest_0 [ create_bd_cell -type ip -vlnv user.org:user:fasec_hwtest:3.2.2 fasec_hwtest_0 ]
set_property -dict [ list \
CONFIG.g_FMC1 {EDA-03287} \
CONFIG.g_FMC2 {EDA-03287} \
......
FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0.xml
View file @ e3139120
......@@ -1055,7 +1055,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu May 11 14:53:08 UTC 2017</spirit:value>
<spirit:value>Thu May 11 16:13:28 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
......@@ -1085,7 +1085,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu May 11 14:53:08 UTC 2017</spirit:value>
<spirit:value>Thu May 11 16:13:28 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
......@@ -1116,7 +1116,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu May 11 14:53:08 UTC 2017</spirit:value>
<spirit:value>Thu May 11 16:13:28 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
......@@ -1162,7 +1162,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu May 11 14:53:08 UTC 2017</spirit:value>
<spirit:value>Thu May 11 16:13:28 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
......@@ -1193,7 +1193,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu May 11 14:53:08 UTC 2017</spirit:value>
<spirit:value>Thu May 11 16:13:28 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
......
FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1.xml
View file @ e3139120
......@@ -1055,7 +1055,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu May 11 14:53:08 UTC 2017</spirit:value>
<spirit:value>Thu May 11 16:13:28 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
......@@ -1085,7 +1085,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu May 11 14:53:08 UTC 2017</spirit:value>
<spirit:value>Thu May 11 16:13:28 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
......@@ -1116,7 +1116,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu May 11 14:53:08 UTC 2017</spirit:value>
<spirit:value>Thu May 11 16:13:28 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
......@@ -1162,7 +1162,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu May 11 14:53:08 UTC 2017</spirit:value>
<spirit:value>Thu May 11 16:13:28 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
......@@ -1193,7 +1193,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu May 11 14:53:08 UTC 2017</spirit:value>
<spirit:value>Thu May 11 16:13:28 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
......
FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2.xml
View file @ e3139120
......@@ -1055,7 +1055,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu May 11 14:53:08 UTC 2017</spirit:value>
<spirit:value>Thu May 11 16:13:28 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
......@@ -1085,7 +1085,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu May 11 14:53:08 UTC 2017</spirit:value>
<spirit:value>Thu May 11 16:13:28 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
......@@ -1116,7 +1116,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu May 11 14:53:08 UTC 2017</spirit:value>
<spirit:value>Thu May 11 16:13:28 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
......@@ -1162,7 +1162,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu May 11 14:53:08 UTC 2017</spirit:value>
<spirit:value>Thu May 11 16:13:28 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
......@@ -1193,7 +1193,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu May 11 14:53:08 UTC 2017</spirit:value>
<spirit:value>Thu May 11 16:13:28 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
......
FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd
View file @ e3139120
......@@ -46,8 +46,8 @@
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: user.org:user:fasec_hwtest:3.2.1
-- IP Revision: 29
-- IP VLNV: user.org:user:fasec_hwtest:3.2.2
-- IP Revision: 30
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
......
FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/synth/system_design_fasec_hwtest_0_0.vhd
View file @ e3139120
......@@ -46,8 +46,8 @@
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: user.org:user:fasec_hwtest:3.2.1
-- IP Revision: 29
-- IP VLNV: user.org:user:fasec_hwtest:3.2.2
-- IP Revision: 30
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
......
FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0.xci
View file @ e3139120
......@@ -7,7 +7,7 @@
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>system_design_fasec_hwtest_0_0</spirit:instanceName>
<spirit:componentRef spirit:vendor="user.org" spirit:library="user" spirit:name="fasec_hwtest" spirit:version="3.2.1"/>
<spirit:componentRef spirit:vendor="user.org" spirit:library="user" spirit:name="fasec_hwtest" spirit:version="3.2.2"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.ADDR_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
......@@ -61,7 +61,7 @@
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">29</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">30</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
......
FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd → FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_2/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd
View file @ e3139120
......@@ -65,9 +65,9 @@ entity general_fmc is
FMC_CLK0C2M_P_o : out std_logic;
FMC_CLK0C2M_N_o : out std_logic;
-- FMC general purpose
FMC_GP0_i : in std_logic;
FMC_GP1_i : in std_logic;
FMC_GP2_i : in std_logic;
FMC_GP0_i : in std_logic;
FMC_GP1_i : in std_logic;
FMC_GP2_i : in std_logic;
FMC_GP3_b : inout std_logic;
-- generic registers for passing data to top module
-- rw data, modified by master
......@@ -93,12 +93,16 @@ architecture rtl of general_fmc is
constant c_COUNTERWIDTH : positive := 24;
constant c_LEDCOUNTERWIDTH : positive := 32;
-- memory mapping EDA-03287:
constant c_ADDR_COMPIN : positive := 16#00#;
constant c_ADDR_COMPEXIN : positive := 16#04#;
constant c_ADDR_OUTEXIN : positive := 16#05#;
-- 0x00 : General Purpose
-- 0x00 ro : bit19-0 comparator input status
-- 0x01 ro : bit3-0 output feedback status
-- 0x02 rw : bit7-0 output request
-- 0x03 rw : DAC control (see dac7716_spi.vhd)
-- 0x04 ro : bit19-0 extended input status for LEDs
-- 0x05 ro : bit7-0 extended output status for LEDs
-- 0x08 rw : 20x channel write request
-- 0x1C ro : 20x channel read values
-- 0x30 ro : 20x pulse length counter (assserted pulse)
......@@ -112,7 +116,7 @@ architecture rtl of general_fmc is
type t_cmplengths is array (0 to c_COMP-1) of std_logic_vector(c_COUNTERWIDTH-1 downto 0);
signal s_cmp_lengths : t_cmplengths;
signal s_diffouts_o : std_logic_vector(c_DOUTS-1 downto 0);
signal s_outleds : std_logic_vector(c_DOUTS-1 downto 0);
signal s_outleds : std_logic_vector(c_DOUTS-1 downto 0);
signal s_outsfeedbak_i : std_logic_vector(c_OUTFBD-1 downto 0);
signal s_spi_sclk : std_logic;
signal s_spi_mosi : std_logic;
......@@ -286,10 +290,10 @@ begin
end generate gen_clkouts;
p_fmc_03287_io : process(clk_i)
variable v_cmp : std_logic_vector(c_COMP-1 downto 0);
variable v_cmpled : std_logic_vector(c_COMP-1 downto 0);
variable v_dout : std_logic_vector(c_DOUTS-1 downto 0);
variable v_fbd : std_logic_vector(c_OUTFBD-1 downto 0);
variable v_cmp : std_logic_vector(c_COMP-1 downto 0);
variable v_cmpled : std_logic_vector(c_COMP-1 downto 0);
variable v_dout : std_logic_vector(c_DOUTS-1 downto 0);
variable v_fbd : std_logic_vector(c_OUTFBD-1 downto 0);
variable v_outleds : std_logic_vector(c_DOUTS-1 downto 0);
begin
if g_FMC = "EDA-03287" and rising_edge(clk_i) then
......@@ -311,15 +315,16 @@ begin
intr_led_o <= '0';
end if;
-- clocking in data for above interrupt generation
v_cmpled := s_compleds(c_COMP-1 downto 0);
v_cmp := s_cmp_pulse(c_COMP-1 downto 0);
v_outleds := s_outleds(c_DOUTS-1 downto 0);
-- leds combination from status and extended pulse
v_cmp := s_cmp_pulse(c_COMP-1 downto 0);
v_cmpled := s_compleds(c_COMP-1 downto 0) or s_cmp_pulse(c_COMP-1 downto 0);
v_outleds := s_outleds(c_DOUTS-1 downto 0) or v_dout(c_DOUTS-1 downto 0);
end if;
end process p_fmc_03287_io;
-- no additional clocking of comparators & LEDs
data_o(0) <= resize(unsigned(s_cmp_pulse), data_o(0)'length);
data_o(4) <= resize(unsigned(s_compleds), data_o(0)'length);
data_o(c_ADDR_COMPIN) <= resize(unsigned(s_cmp_pulse), data_o(0)'length);
data_o(c_ADDR_COMPEXIN) <= resize(unsigned(s_compleds), data_o(0)'length);
data_o(c_ADDR_OUTEXIN) <= resize(unsigned(s_outleds), data_o(0)'length);
--=============================================================================
-- EDA-02327: FMC user lines - clock in for AXI register read by Zynq PS
--=============================================================================
......
FASEC_prototype.srcs/sources_1/bd/system_design/system_design.bd
View file @ e3139120
......@@ -727,7 +727,7 @@
</spirit:componentInstance>
<spirit:componentInstance>
<spirit:instanceName>fasec_hwtest_0</spirit:instanceName>
<spirit:componentRef spirit:library="user" spirit:name="fasec_hwtest" spirit:vendor="user.org" spirit:version="3.2.1"/>
<spirit:componentRef spirit:library="user" spirit:name="fasec_hwtest" spirit:vendor="user.org" spirit:version="3.2.2"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="bd:xciName">system_design_fasec_hwtest_0_0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="g_FMC1">EDA-03287</spirit:configurableElementValue>
......
FASEC_prototype.srcs/sources_1/bd/system_design/system_design.bxml
View file @ e3139120
......@@ -2,9 +2,9 @@
<Root MajorVersion="0" MinorVersion="33">
<CompositeFile CompositeFileTopName="system_design" CanBeSetAsTop="true" CanDisplayChildGraph="true">
<Description>Composite Fileset</Description>
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1494514392"/>
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1494514392"/>
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1494514392"/>
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1494519212"/>
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1494519212"/>
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1494519212"/>
<FileCollection Name="SOURCES" Type="SOURCES">
<File Name="ip/system_design_processing_system7_0_0/system_design_processing_system7_0_0.xci" Type="IP">
<Instance HierarchyPath="processing_system7_0"/>
......@@ -23,6 +23,7 @@
<UsedIn Val="SIMULATION"/>
</File>
<File Name="ip/system_design_processing_system7_0_axi_periph_3/system_design_processing_system7_0_axi_periph_3.xci" Type="IP">
<Instance HierarchyPath="processing_system7_0_axi_periph"/>
<Properties IsEditable="false" IsVisible="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
......@@ -78,6 +79,7 @@
<UsedIn Val="SIMULATION"/>
</File>
<File Name="ip/system_design_axi_interconnect_0_0/system_design_axi_interconnect_0_0.xci" Type="IP">
<Instance HierarchyPath="axi_interconnect_0"/>
<Properties IsEditable="false" IsVisible="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
......@@ -141,6 +143,7 @@
<UsedIn Val="SIMULATION"/>
</File>
<File Name="ip/system_design_axi_interconnect_1_0/system_design_axi_interconnect_1_0.xci" Type="IP">
<Instance HierarchyPath="axi_interconnect_1"/>
<Properties IsEditable="false" IsVisible="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
......
FASEC_prototype.xpr
View file @ e3139120
......@@ -36,13 +36,13 @@
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="77"/>
<Option Name="WTModelSimExportSim" Val="77"/>
<Option Name="WTQuestaExportSim" Val="77"/>
<Option Name="WTIesExportSim" Val="77"/>
<Option Name="WTVcsExportSim" Val="77"/>
<Option Name="WTRivieraExportSim" Val="77"/>
<Option Name="WTActivehdlExportSim" Val="77"/>
<Option Name="WTXSimExportSim" Val="78"/>
<Option Name="WTModelSimExportSim" Val="78"/>
<Option Name="WTQuestaExportSim" Val="78"/>
<Option Name="WTIesExportSim" Val="78"/>
<Option Name="WTVcsExportSim" Val="78"/>
<Option Name="WTRivieraExportSim" Val="78"/>
<Option Name="WTActivehdlExportSim" Val="78"/>
</Configuration>
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
......@@ -53,25 +53,25 @@
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_rst_processing_system7_0_100M_2/system_design_rst_processing_system7_0_100M_2.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xlconstant_6_0/system_design_xlconstant_6_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_axi_uartlite_0_0/system_design_axi_uartlite_0_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_rst_wrc_1p_kintex7_0_62M_0/system_design_rst_wrc_1p_kintex7_0_62M_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_axi_interconnect_1_0/system_design_axi_interconnect_1_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="hdl/system_design.vhd"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_wrc_1p_kintex7_0_0/system_design_wrc_1p_kintex7_0_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xlconcat_0_0/system_design_xlconcat_0_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_axi_interconnect_0_0/system_design_axi_interconnect_0_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_axi_dma_0_0/system_design_axi_dma_0_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xadc_axis_fifo_adapter_0_0/system_design_xadc_axis_fifo_adapter_0_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xadc_wiz_0_0/system_design_xadc_wiz_0_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xlconstant_3_2/system_design_xlconstant_3_2.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xbar_0/system_design_xbar_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_processing_system7_0_axi_periph_3/system_design_processing_system7_0_axi_periph_3.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_rst_processing_system7_0_100M_2/system_design_rst_processing_system7_0_100M_2.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xbar_0/system_design_xbar_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xlconstant_3_2/system_design_xlconstant_3_2.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_processing_system7_0_0/system_design_processing_system7_0_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_processing_system7_0_axi_periph_3/system_design_processing_system7_0_axi_periph_3.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="hdl/system_design.vhd"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_axi_interconnect_1_0/system_design_axi_interconnect_1_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_rst_wrc_1p_kintex7_0_62M_0/system_design_rst_wrc_1p_kintex7_0_62M_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xlconstant_6_0/system_design_xlconstant_6_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xadc_wiz_0_0/system_design_xadc_wiz_0_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xadc_axis_fifo_adapter_0_0/system_design_xadc_axis_fifo_adapter_0_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_axi_dma_0_0/system_design_axi_dma_0_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_axi_interconnect_0_0/system_design_axi_interconnect_0_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xlconcat_0_0/system_design_xlconcat_0_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_axi_uartlite_0_0/system_design_axi_uartlite_0_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0.xci"/>
</File>
<File Path="$PSRCDIR/sources_1/bd/system_design/hdl/system_design_wrapper.vhd">
<FileInfo>
......@@ -134,14 +134,13 @@
</Simulator>
</Simulators>
<Runs Version="1" Minor="10">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z030ffg676-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z030ffg676-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2016"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z030ffg676-2" ConstrsSet="constrs_1" Description="Default settings for Implementation." State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true">
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z030ffg676-2" ConstrsSet="constrs_1" Description="Default settings for Implementation." State="current" SynthRun="synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2016"/>
<Step Id="init_design"/>
......@@ -154,7 +153,6 @@
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream" PostStepTclHook="$PSRCDIR/tcl/copy_bitstream.tcl"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
</Run>
</Runs>
</Project>
cores @ 4d140106
Subproject commit 82fbf1fa8af7179fe798230320cb5b60ef95ae39
Subproject commit 4d1401068918b0f8d8b661925959b0da2f522c19
ip_upgrade.log
View file @ e3139120
Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
| Date : Thu May 11 18:13:15 2017
| Host : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command : upgrade_ip
| Device : xc7z030ffg676-2
------------------------------------------------------------------------------------
Upgrade Log for IP 'system_design_fasec_hwtest_0_0'
1. Summary
----------
SUCCESS in the upgrade of system_design_fasec_hwtest_0_0 from user.org:user:fasec_hwtest:3.2.1 (Rev. 29) to user.org:user:fasec_hwtest:3.2.2 (Rev. 30)
Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
......
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