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FPGA and ARM SoC FMC Carrier FASEC
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Projects
FPGA and ARM SoC FMC Carrier FASEC
Commits
bc0eb056
Commit
bc0eb056
authored
May 11, 2017
by
Pieter Van Trappen
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submodule cores updated for fasec_hwtest
parent
bbdc1b6c
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2 changed files
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1 addition
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27 deletions
+1
-27
FASEC_prototype.xpr
FASEC_prototype.xpr
+0
-26
cores
ip_cores/cores
+1
-1
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FASEC_prototype.xpr
View file @
bc0eb056
...
...
@@ -53,32 +53,6 @@
<Attr
Name=
"UsedIn"
Val=
"implementation"
/>
<Attr
Name=
"UsedIn"
Val=
"simulation"
/>
</FileInfo>
<CompFileExtendedInfo
CompFileName=
"system_design.bd"
FileRelPathName=
"ip/system_design_rst_processing_system7_0_100M_2/system_design_rst_processing_system7_0_100M_2.xci"
/>
<CompFileExtendedInfo
CompFileName=
"system_design.bd"
FileRelPathName=
"ip/system_design_processing_system7_0_0/system_design_processing_system7_0_0.xci"
/>
<CompFileExtendedInfo
CompFileName=
"system_design.bd"
FileRelPathName=
"ip/system_design_axi_interconnect_1_0/system_design_axi_interconnect_1_0.xci"
/>
<CompFileExtendedInfo
CompFileName=
"system_design.bd"
FileRelPathName=
"ip/system_design_rst_wrc_1p_kintex7_0_62M_0/system_design_rst_wrc_1p_kintex7_0_62M_0.xci"
/>
<CompFileExtendedInfo
CompFileName=
"system_design.bd"
FileRelPathName=
"ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1.xci"
/>
<CompFileExtendedInfo
CompFileName=
"system_design.bd"
FileRelPathName=
"ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0.xci"
/>
<CompFileExtendedInfo
CompFileName=
"system_design.bd"
FileRelPathName=
"ip/system_design_xlconstant_6_0/system_design_xlconstant_6_0.xci"
/>
<CompFileExtendedInfo
CompFileName=
"system_design.bd"
FileRelPathName=
"ip/system_design_axi_uartlite_0_0/system_design_axi_uartlite_0_0.xci"
/>
<CompFileExtendedInfo
CompFileName=
"system_design.bd"
FileRelPathName=
"ip/system_design_wrc_1p_kintex7_0_0/system_design_wrc_1p_kintex7_0_0.xci"
/>
<CompFileExtendedInfo
CompFileName=
"system_design.bd"
FileRelPathName=
"ip/system_design_xlconcat_0_0/system_design_xlconcat_0_0.xci"
/>
<CompFileExtendedInfo
CompFileName=
"system_design.bd"
FileRelPathName=
"ip/system_design_axi_interconnect_0_0/system_design_axi_interconnect_0_0.xci"
/>
<CompFileExtendedInfo
CompFileName=
"system_design.bd"
FileRelPathName=
"ip/system_design_axi_dma_0_0/system_design_axi_dma_0_0.xci"
/>
<CompFileExtendedInfo
CompFileName=
"system_design.bd"
FileRelPathName=
"ip/system_design_xadc_axis_fifo_adapter_0_0/system_design_xadc_axis_fifo_adapter_0_0.xci"
/>
<CompFileExtendedInfo
CompFileName=
"system_design.bd"
FileRelPathName=
"ip/system_design_xadc_wiz_0_0/system_design_xadc_wiz_0_0.xci"
/>
<CompFileExtendedInfo
CompFileName=
"system_design.bd"
FileRelPathName=
"ip/system_design_xlconstant_3_2/system_design_xlconstant_3_2.xci"
/>
<CompFileExtendedInfo
CompFileName=
"system_design.bd"
FileRelPathName=
"ip/system_design_xbar_0/system_design_xbar_0.xci"
/>
<CompFileExtendedInfo
CompFileName=
"system_design.bd"
FileRelPathName=
"ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0.xci"
/>
<CompFileExtendedInfo
CompFileName=
"system_design.bd"
FileRelPathName=
"ip/system_design_processing_system7_0_axi_periph_3/system_design_processing_system7_0_axi_periph_3.xci"
/>
<CompFileExtendedInfo
CompFileName=
"system_design.bd"
FileRelPathName=
"hdl/system_design.hwdef"
/>
<CompFileExtendedInfo
CompFileName=
"system_design.bd"
FileRelPathName=
"hw_handoff/system_design.hwh"
/>
<CompFileExtendedInfo
CompFileName=
"system_design.bd"
FileRelPathName=
"hw_handoff/system_design_bd.tcl"
/>
<CompFileExtendedInfo
CompFileName=
"system_design.bd"
FileRelPathName=
"ip/system_design_auto_pc_0/system_design_auto_pc_0.xci"
/>
<CompFileExtendedInfo
CompFileName=
"system_design.bd"
FileRelPathName=
"ip/system_design_auto_pc_1/system_design_auto_pc_1.xci"
/>
<CompFileExtendedInfo
CompFileName=
"system_design.bd"
FileRelPathName=
"ip/system_design_auto_pc_2/system_design_auto_pc_2.xci"
/>
<CompFileExtendedInfo
CompFileName=
"system_design.bd"
FileRelPathName=
"hdl/system_design.vhd"
/>
<CompFileExtendedInfo
CompFileName=
"system_design.bd"
FileRelPathName=
"system_design_ooc.xdc"
/>
</File>
<File
Path=
"$PSRCDIR/sources_1/bd/system_design/hdl/system_design_wrapper.vhd"
>
<FileInfo>
...
...
cores
@
82fbf1fa
Subproject commit
1adb5f14d49f161e30e0b2e33b7601fddaecc90a
Subproject commit
82fbf1fa8af7179fe798230320cb5b60ef95ae39
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