Commit 9d6b80c3 authored by garcialasheras's avatar garcialasheras

Some tweaks to synthesis scripts

parent a51e8d1f
#!/bin/bash
planAhead -mode tcl -source create_project.tcl
create_project project_demo /home/javi/project_demo -part xc7z020clg484-1
create_project project_zed ./project_zed -part xc7z020clg484-1
set_property board zedBoard [current_project]
set_property target_language VHDL [current_project]
set_property ng.output_hdl_format VHDL [get_filesets sim_1]
add_files -norecurse /home/javi/Escritorio/Xilinx/ZedBoard_Linux_Design/hw/xps_proj/system.xmp
add_files -norecurse /home/javi/Escritorio/Xilinx/top/system_stub.vhd
add_files -norecurse ../../modules/system/system.xmp
add_files -norecurse ../../top/zed_1/zed_top.vhd
add_files -norecurse ../../top/zed_1/zed_top.ucf
add_files -norecurse ../../ip_cores/asyncart/hdl/asyncart_reg.vhd
add_files -norecurse ../../ip_cores/asyncart/hdl/asyncart_sink.vhd
add_files -norecurse ../../ip_cores/asyncart/hdl/asyncart_source.vhd
add_files -norecurse ../../ip_cores/asyncart/hdl/asyncart_demo.vhd
update_compile_order -fileset sources_1
update_compile_order -fileset sim_1
add_files -norecurse /home/javi/Escritorio/Xilinx/synthesis_zedboard_async/asyncart_reg.vhd
set_property top zed_top [get_property srcset [current_run]]
update_compile_order -fileset sources_1
set_property top system_stub
update_compile_order -fileset sim_1
exit
open_project /home/javi/project_make/project_make.ppr
open_project ./project_zed/project_zed.ppr
reset_run synth_1
reset_run impl_1
launch_runs synth_1 -jobs 4
launch_runs synth_1
wait_on_run synth_1
launch_runs impl_1 -jobs 4
launch_runs impl_1
wait_on_run impl_1
launch_runs impl_1 -to_step Bitgen
exit
......
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