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Euro ADC 65M 14b 40cha hw PUMA-hw
Commit a928cae4 authored by David Cussans's avatar David Cussans
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Updated CPLD code for pc051c: 

- Put back in over temp shutdown
- Register data in I2C and SPI busses with 10MHz clock 
- Put back power on/off by HDMI
parent 097823cb
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Showing with 67 additions and 57 deletions
firmware/CPLD/src/pc051b_cpld.vhd
View file @ a928cae4
......@@ -56,7 +56,8 @@ entity Multiplexer is
clk_in : in std_logic; -- Needed for SPI slave in CPLD and power on-off / thermal shutdown
temp_Alarm_i : in std_logic ; -- Driven low by temp monitor if board overheats
-- temp_Alarm_i : in std_logic ; -- Driven low by temp monitor if board overheats
temp_Alarm_i : inout std_logic ; ---- bodge
temp_Alarm_Led_o : out std_logic ; -- goes high if CPLD shuts down due to over temperature
POR_i : in std_logic ; -- driven low by power-on-reset chip when power cycled. Causes PGood_o and FPGA_Power_Enable_o to drop low
PGood_from_FPGA_i : in std_logic; -- goes high when power rails are up and stable on FPGA
......@@ -151,7 +152,8 @@ begin
-- temp_Alarm_Led_o <= s_powerSwitch;
--temp_Alarm_Led_o <= POR_i;
-- temp_Alarm_Led_o <= PGood_from_HDMI_i ;
temp_Alarm_Led_o <= temp_Alarm_i;
--temp_Alarm_Led_o <= temp_Alarm_i;
temp_Alarm_i <= clk_in;
-- Bodge - prevent optimization
process (clk_in)
......
firmware/CPLD/src/pc051c_cpld.ucf
View file @ a928cae4
......@@ -100,10 +100,10 @@ NET "SFP_tx_fault<0>" LOC = "F2" |IOSTANDARD = LVCMOS33 ;
NET "SFP_present<1>" LOC = "G3" |IOSTANDARD = LVCMOS33 ;
NET "SFP_tx_fault<1>" LOC = "H3" |IOSTANDARD = LVCMOS33 ;
NET "cpld_led<1>" LOC = "H2" |IOSTANDARD = LVCMOS33 ;
NET "cpld_led<0>" LOC = "E2" |IOSTANDARD = LVCMOS33 ;
NET "cpld_led<2>" LOC = "E1" |IOSTANDARD = LVCMOS33 ;
NET "cpld_led<3>" LOC = "F1" |IOSTANDARD = LVCMOS33 ;
NET "cpld_leds_o<1>" LOC = "H2" | IOSTANDARD = LVCMOS33;
NET "cpld_leds_o<0>" LOC = "E2" | IOSTANDARD = LVCMOS33 ;
#NET "cpld_leds_o<2>" LOC = "E1" ;
#NET "cpld_leds_o<3>" LOC = "F1" ;
NET "CLK_IN" LOC = "P5" ;
......@@ -115,8 +115,8 @@ NET "PGood_from_HDMI_i" LOC = "C7" |IOSTANDARD = LVCMOS33 ;
NET "FPGA_Power_Enable_o" LOC = "B3" |IOSTANDARD = LVCMOS33 ;
NET "PGood_o" LOC = "F3" |IOSTANDARD = LVCMOS33 ;
NET "PGood3v3_o" LOC = "B7" | IOSTANDARD = LVCMOS33 ;
NET "power_switch_high_on" LOC = "C3" |IOSTANDARD = LVCMOS33 ;
NET "power_switch_high_off" LOC = "E3" |IOSTANDARD = LVCMOS33 ;
NET "power_switch_high_on" LOC = "C3" |IOSTANDARD = LVCMOS33 | PULLUP;
NET "power_switch_high_off" LOC = "E3" |IOSTANDARD = LVCMOS33 | PULLUP ;
NET "fpga_en1" LOC = "B4" |IOSTANDARD = LVCMOS33 ;
NET "fpga_resin" LOC = "B5" |IOSTANDARD = LVCMOS33 ;
NET "GPIO<0>" LOC = "E14" |IOSTANDARD = LVCMOS33 ;
......
firmware/CPLD/src/pc051c_cpld.vhd
View file @ a928cae4
......@@ -10,9 +10,11 @@ use IEEE.numeric_std.all;
entity Multiplexer is
generic (
g_NUM_SPI : natural := 8; -- Number of SPI devices
g_NUM_I2C : natural := 10;
g_NUM_SFP : natural := 2); -- number of I2C busses
g_NUM_SPI : natural := 8; -- Number of SPI devices
g_NUM_I2C : natural := 10; -- number of I2C busses
g_NUM_SFP : natural := 2; -- number of SFP cages
g_NUM_LEDS: natural := 2 -- number of LEDs connected to CPLD
);
port (
-- SPI busses to ADC chips
......@@ -56,10 +58,11 @@ entity Multiplexer is
clk_in : in std_logic; -- Needed for SPI slave in CPLD and power on-off / thermal shutdown
temp_Alarm_i : in std_logic ; -- Driven high by temp monitor if board overheats
temp_Alarm_i : in std_logic ; -- Driven low by temp monitor if board overheats
temp_Alarm_Led_o : out std_logic ; -- goes high if CPLD shuts down due to over temperature
cpld_leds_o : out std_logic_vector(g_NUM_LEDS-1 downto 0);
POR_i : in std_logic ; -- driven high by power-on-reset chip. Causes PGood_o and FPGA_Power_Enable_o to drop low
PGood_from_FPGA_i : in std_logic; -- goes high when power rails are up and stable on FPGA
PGood_from_FPGA_i : in std_logic; -- goes high when power rails are up and stable on FPGA
PGood_from_HDMI_i : in std_logic; -- goes high when power enabled by off-board control
FPGA_Power_Enable_o : out std_logic; -- goes high to enable DC-DC converters on Trenz FPGA board.
PGood3v3_o : out std_logic; -- goes high to enable the +3.3V supply for FPGA and clock circuit
......@@ -92,6 +95,11 @@ begin
-- bodge
-- bodge CPLD LEDS...
cpld_leds_o(0) <= s_fpgaPowerEnable;
-- cpld_leds_o(1) <= PGood_from_FPGA_i;
cpld_leds_o(1) <= PGood_from_HDMI_i;
--gpio <= ( others => '0');
gpio(4 downto 0) <= bus_select;
--gpio(9 downto 5) <= ( others => '0');
......@@ -110,16 +118,18 @@ begin
-- if power is enabled by front panel switch and HDMI and we haven't overheated.
s_fpgaPowerEnable <= '1' when s_enabled = '1' and s_TempOK = '1' else '0';
-- If we don't want to listen to over-temp use the line below....
-- s_fpgaPowerEnable <= '1' when s_enabled = '1' ;
-- permanently enable power....
--FPGA_Power_Enable_o <= s_fpgaPowerEnable; -- raise the power enable pin on FPGA
--PGood3v3_o <= s_fpgaPowerEnable; -- turn on the 3.3V power for FPGA and clock. Might want delay.
FPGA_Power_Enable_o <= '1';
PGood3v3_o <= '1';
FPGA_Power_Enable_o <= s_fpgaPowerEnable;
PGood3v3_o <= s_fpgaPowerEnable;
-- Once FPGA has turned on its DC-DC converters, turn on regulators on board.
-- PGood_o <= '1' when PGood_from_FPGA_i = '1' and s_enabled = '1' and s_TempOK = '1' else '0';
PGood_o <= '1';
PGood_o <= s_fpgaPowerEnable;
-- Set JTAGEN ( fpga_en1) low for normal operation. Only need to set high to program the Lattice Mach02 CPLD on Trenz TE0712
fpga_en1 <='0';
......@@ -127,11 +137,7 @@ begin
-- set RESIN high for normal operations. (Pulling low will reconfigure the FPGA )
fpga_resin <='1';
-- temp_Alarm_Led_o <='1' when s_TempOK = '0' else '0' ;
-- Bodge
--temp_Alarm_Led_o <= power_switch_high_on;
--s_powerSwitch ;
temp_Alarm_Led_o <= bus_select(1);
temp_Alarm_Led_o <= not temp_Alarm_i;
-- Bodge - prevent optimization
process (clk_in)
......@@ -146,7 +152,7 @@ end process;
process (clk_in)
begin
if rising_edge(clk_in) then
if POR_i = '1' then
if POR_i = '0' then
s_powerSwitch <= '0';
elsif power_switch_high_on = '1' then
s_powerSwitch <= '1';
......@@ -160,11 +166,11 @@ end process;
process (clk_in)
begin
if rising_edge(clk_in) then
if POR_i = '1' then
if POR_i = '0' then
s_TempOK <= '1';
elsif temp_Alarm_i = '1' then
elsif temp_Alarm_i = '0' then
s_TempOK <= '0';
elsif temp_Alarm_i = '0' and s_enabled = '0' then -- Only reset when power cycled.
elsif temp_Alarm_i = '1' and s_enabled = '0' then -- Only reset when power cycled.
s_TempOK <= '1';
end if;
end if;
......@@ -179,50 +185,52 @@ SPI_number <= to_integer(unsigned(bus_select(3 downto 1)));
-- process
process(bus_select,SDOA_from_ADC,SDOB_from_ADC,SDA_I2C,SDO_from_FPGA,SCK_from_FPGA,SDA_out_from_FPGA,SCL_from_FPGA,bus_select_int,SPI_number,SPI_CSN_FROM_FPGA)
process(bus_select,SDOA_from_ADC,SDOB_from_ADC,SDA_I2C,SDO_from_FPGA,SCK_from_FPGA,SDA_out_from_FPGA,SCL_from_FPGA,bus_select_int,SPI_number,SPI_CSN_FROM_FPGA,clk_in)
begin
if rising_edge(clk_in) then
-- Initialization
-- Initialization
SDI_to_FPGA <= '0';
SCK_to_ADC <= (others => '0');
SDI_to_ADC <= (others => '0');
CSA_to_ADC <= (others => '1');
CSB_to_ADC <= (others => '1');
SDI_to_FPGA <= '0';
SCK_to_ADC <= (others => '0');
SDI_to_ADC <= (others => '0');
CSA_to_ADC <= (others => '1');
CSB_to_ADC <= (others => '1');
SCL_to_I2C <= (others => 'Z');
s_SDA_in_to_FPGA <= '1';
SDA_I2C <= (others => 'Z');
SCL_to_I2C <= (others => 'Z');
s_SDA_in_to_FPGA <= '1';
SDA_I2C <= (others => 'Z');
-- SPI
-- SPI
if(SPI_CSN_FROM_FPGA = '0') then
SDI_to_ADC(SPI_number) <= SDO_from_FPGA;
SCK_to_ADC(SPI_number) <= SCK_from_FPGA;
if (bus_select(0) = '0') then
SDI_to_FPGA <= SDOA_from_ADC(SPI_number);
CSA_to_ADC(SPI_number) <= '0';
else
SDI_to_FPGA <= SDOB_from_ADC(SPI_number);
CSB_to_ADC(SPI_number) <= '0';
if(SPI_CSN_FROM_FPGA = '0') then
SDI_to_ADC(SPI_number) <= SDO_from_FPGA;
SCK_to_ADC(SPI_number) <= SCK_from_FPGA;
if (bus_select(0) = '0') then
SDI_to_FPGA <= SDOA_from_ADC(SPI_number);
CSA_to_ADC(SPI_number) <= '0';
else
SDI_to_FPGA <= SDOB_from_ADC(SPI_number);
CSB_to_ADC(SPI_number) <= '0';
end if;
end if;
end if;
-- I2C
-- I2C
if(bus_select_int < (g_NUM_I2C+1)) then -- only 9 I2C
if (SDA_out_from_FPGA = '0') then
SDA_I2C(bus_select_int) <= '0';
else
SDA_I2C(bus_select_int) <= 'Z';
end if;
if(bus_select_int < (g_NUM_I2C+1)) then -- only 9 I2C
if (SDA_out_from_FPGA = '0') then
SDA_I2C(bus_select_int) <= '0';
else
SDA_I2C(bus_select_int) <= 'Z';
end if;
s_SDA_in_to_FPGA <= TO_X01(SDA_I2C(bus_select_int));
SCL_to_I2C(bus_select_int) <= SCL_from_FPGA;
end if;
s_SDA_in_to_FPGA <= TO_X01(SDA_I2C(bus_select_int));
SCL_to_I2C(bus_select_int) <= SCL_from_FPGA;
end if;
end if;
end process;
end Multiplexer_arch;
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