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Euro ADC 65M 14b 40cha hw PUMA-hw
Commit 723c62fe authored by David Cussans's avatar David Cussans
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Checking in CPLD firmware with 'stelth option' added

parent 3d9a0387
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firmware/CPLD/hdl_designer/pc051b_cpld.hdp 0 → 100644
View file @ 723c62fe
[QuestaSim]
pc051b_cpld_lib = $HDS_PROJECT_DIR/pc051b_cpld_lib/work
[hdl]
pc051b_cpld_lib = $HDS_PROJECT_DIR/pc051b_cpld_lib/hdl
[hds]
pc051b_cpld_lib = $HDS_PROJECT_DIR/pc051b_cpld_lib/hds
[hds_settings]
default_library = pc051b_cpld_lib
version = 2
[library_type]
pc051b_cpld_lib = regular
[shared]
others = $HDS_TEAM_HOME/shared.hdp
firmware/CPLD/hdl_designer/pc051b_cpld_lib/hdl/i2c_deglitch_fsm.vhd 0 → 100644
View file @ 723c62fe
-- VHDL Entity pc051b_cpld_lib.i2c_deglitch.symbol
--
-- Created:
-- by - phdgc.users (voltar.phy.bris.ac.uk)
-- at - 09:17:34 03/13/17
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2015.1b (Build 4)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY i2c_deglitch IS
PORT(
clk : IN std_logic;
din : IN std_logic;
rst : IN std_logic;
dout : OUT std_logic
);
-- Declarations
END ENTITY i2c_deglitch ;
--
-- VHDL Architecture pc051b_cpld_lib.i2c_deglitch.fsm
--
-- Created:
-- by - phdgc.users (voltar.phy.bris.ac.uk)
-- at - 09:17:33 03/13/17
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2015.1b (Build 4)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ARCHITECTURE fsm OF i2c_deglitch IS
TYPE STATE_TYPE IS (
low,
waiting_for_high,
high,
waiting_for_low
);
-- Declare current and next state signals
SIGNAL current_state : STATE_TYPE;
SIGNAL next_state : STATE_TYPE;
BEGIN
-----------------------------------------------------------------
clocked_proc : PROCESS (
clk
)
-----------------------------------------------------------------
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF (rst = '1') THEN
current_state <= high;
ELSE
current_state <= next_state;
END IF;
END IF;
END PROCESS clocked_proc;
-----------------------------------------------------------------
nextstate_proc : PROCESS (
current_state,
din
)
-----------------------------------------------------------------
BEGIN
CASE current_state IS
WHEN low =>
IF (din = '1') THEN
next_state <= waiting_for_high;
ELSIF (din = '0') THEN
next_state <= low;
ELSE
next_state <= low;
END IF;
WHEN waiting_for_high =>
IF (din = '0') THEN
next_state <= low;
ELSIF (din = '1') THEN
next_state <= high;
ELSE
next_state <= waiting_for_high;
END IF;
WHEN high =>
IF (din = '0') THEN
next_state <= waiting_for_low;
ELSIF (din = '1') THEN
next_state <= high;
ELSE
next_state <= high;
END IF;
WHEN waiting_for_low =>
IF (din = '1') THEN
next_state <= high;
ELSIF (din = '0') THEN
next_state <= low;
ELSE
next_state <= waiting_for_low;
END IF;
WHEN OTHERS =>
next_state <= high;
END CASE;
END PROCESS nextstate_proc;
-----------------------------------------------------------------
output_proc : PROCESS (
current_state
)
-----------------------------------------------------------------
BEGIN
-- Combined Actions
CASE current_state IS
WHEN low =>
dout <= '0';
WHEN waiting_for_high =>
dout <= '0';
WHEN high =>
dout <= '1';
WHEN waiting_for_low =>
dout <= '1';
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS output_proc;
END ARCHITECTURE fsm;
firmware/CPLD/hdl_designer/pc051b_cpld_lib/hds/.xrf/i2c_deglitch_fsm.xrf 0 → 100644
View file @ 723c62fe
DESIGN i2c_deglitch
VIEW symbol.sb
NO_GRAPHIC 0
DESIGN i2c_deglitch
VIEW symbol.sb
GRAPHIC 50,0 8 0
DESIGN i2c_deglitch
VIEW symbol.sb
GRAPHIC 116,0 14 0
DESIGN i2c_deglitch
VIEW symbol.sb
GRAPHIC 131,0 15 0
DESIGN i2c_deglitch
VIEW symbol.sb
GRAPHIC 121,0 16 0
DESIGN i2c_deglitch
VIEW symbol.sb
GRAPHIC 126,0 17 0
DESIGN i2c_deglitch
VIEW symbol.sb
GRAPHIC 1,0 20 0
DESIGN i2c_deglitch
VIEW symbol.sb
GRAPHIC 1,0 21 0
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
GRAPHIC 33,0 33 0
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
NO_GRAPHIC 36
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
GRAPHIC 2,0 53 0
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
NO_GRAPHIC 54
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
GRAPHIC 2,0 56 0
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
NO_GRAPHIC 57
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
GRAPHIC 62,0 58 0
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
GRAPHIC 72,0 59 0
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
NO_GRAPHIC 61
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
GRAPHIC 2,0 65 0
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
NO_GRAPHIC 66
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
GRAPHIC 2,0 68 0
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
NO_GRAPHIC 69
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
GRAPHIC 2,0 74 0
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
GRAPHIC 45,0 75 0
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
GRAPHIC 222,0 76 0
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
GRAPHIC 166,0 77 0
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
GRAPHIC 232,0 78 0
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
GRAPHIC 45,0 79 0
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
NO_GRAPHIC 80
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
GRAPHIC 45,0 81 0
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
NO_GRAPHIC 82
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
GRAPHIC 166,0 83 0
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
GRAPHIC 242,0 84 0
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
GRAPHIC 45,0 85 0
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
GRAPHIC 262,0 86 0
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
GRAPHIC 183,0 87 0
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
NO_GRAPHIC 88
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
GRAPHIC 166,0 89 0
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
NO_GRAPHIC 90
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
GRAPHIC 183,0 91 0
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
GRAPHIC 282,0 92 0
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
GRAPHIC 200,0 93 0
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
GRAPHIC 322,0 94 0
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
GRAPHIC 183,0 95 0
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
NO_GRAPHIC 96
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
GRAPHIC 183,0 97 0
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
NO_GRAPHIC 98
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
GRAPHIC 200,0 99 0
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
GRAPHIC 292,0 100 0
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
GRAPHIC 183,0 101 0
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
GRAPHIC 302,0 102 0
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
GRAPHIC 45,0 103 0
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
NO_GRAPHIC 104
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
GRAPHIC 200,0 105 0
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
NO_GRAPHIC 106
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
GRAPHIC 95,0 107 0
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
NO_GRAPHIC 109
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
GRAPHIC 2,0 110 0
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
NO_GRAPHIC 111
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
GRAPHIC 2,0 113 0
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
NO_GRAPHIC 114
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
GRAPHIC 2,0 120 0
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
GRAPHIC 45,0 121 0
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
GRAPHIC 60,0 122 0
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
GRAPHIC 166,0 123 0
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
GRAPHIC 181,0 124 0
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
GRAPHIC 183,0 125 0
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
GRAPHIC 198,0 126 0
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
GRAPHIC 200,0 127 0
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
GRAPHIC 215,0 128 0
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
NO_GRAPHIC 129
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
GRAPHIC 2,0 131 0
LIBRARY pc051b_cpld_lib
DESIGN i2c_deglitch
VIEW fsm.sm
NO_GRAPHIC 133
firmware/CPLD/hdl_designer/pc051b_cpld_lib/hds/_i2c_deglitch._epf 0 → 100755
View file @ 723c62fe
DEFAULT_ARCHITECTURE atom fsm
DEFAULT_FILE atom i2c_deglitch/fsm.sm
firmware/CPLD/hdl_designer/pc051b_cpld_lib/hds/i2c_deglitch/_fsm.sm._fpf 0 → 100755
View file @ 723c62fe
ARCHITECTURES list {
{i2c_deglitch fsm} list {
TASK_SETTINGS list {
PLUGIN_SETTINGS list {
QuestaSimSimulator atom {TaskSetting Arguments {} TaskSetting Communication 1 TaskSetting DelaySelection typ TaskSetting GlitchGeneration 1 TaskSetting InitCmd {} TaskSetting LogFile {} TaskSetting RemoteHost {} TaskSetting Resolution ns TaskSetting SdfDelay typ TaskSetting SdfMultiSrcDelay latest TaskSetting SdfReduce 0 TaskSetting SdfWarnings 1 TaskSetting TimingChecks 1 TaskSetting UseBatch 0 TaskSetting UseGUI 1 TaskSetting VitalVersion 95 TaskSetting autoNames 1 TaskSetting coverage 0 TaskSetting excludePSL 0 TaskSetting exepath %task_QuestaSimPath TaskSetting minimumSimSetting 0 TaskSetting saveReplayScript 0 TaskSetting useCustomSimDir 0}
}
}
}
}
firmware/CPLD/hdl_designer/pc051b_cpld_lib/work/_info 0 → 100644
View file @ 723c62fe
m255
K4
z2
13
!s112 1.1
!i10d 8192
!i10e 25
!i10f 100
cModel Technology
Z0 d/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/CPLD/hdl_designer/pc051b_cpld_lib/work
Ei2c_deglitch
Z1 w1489396664
Z2 DPx4 ieee 15 std_logic_arith 0 22 [G314=:2zXJ`VORJe1J@Z1
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Z4 DPx4 ieee 14 std_logic_1164 0 22 eNV`TJ_GofJTzYa?f<@Oe1
R0
Z5 8/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/CPLD/hdl_designer/pc051b_cpld_lib/hdl/i2c_deglitch_fsm.vhd
Z6 F/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/CPLD/hdl_designer/pc051b_cpld_lib/hdl/i2c_deglitch_fsm.vhd
l0
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Z11 !s107 /projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/CPLD/hdl_designer/pc051b_cpld_lib/hdl/i2c_deglitch_fsm.vhd|
!i113 0
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firmware/CPLD/hdl_designer/pc051b_cpld_lib/work/modelsim.ini 0 → 100644
View file @ 723c62fe
This diff is collapsed.
firmware/CPLD/src/pc051c_cpld_v0-3.ucf 0 → 100644
View file @ 723c62fe
#PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments
NET "BUS_SELECT<0>" LOC = "C1" | IOSTANDARD = LVCMOS33 ;
NET "BUS_SELECT<1>" LOC = "B1" | IOSTANDARD = LVCMOS33 ;
NET "BUS_SELECT<2>" LOC = "A2" | IOSTANDARD = LVCMOS33 ;
NET "BUS_SELECT<3>" LOC = "A3" | IOSTANDARD = LVCMOS33 ;
NET "BUS_SELECT<4>" LOC = "B9" | IOSTANDARD = LVCMOS33 ;
NET "CSA_to_ADC<0>" LOC = "L1" | IOSTANDARD = LVCMOS18 ;
NET "CSA_to_ADC<1>" LOC = "R1" | IOSTANDARD = LVCMOS18 ;
NET "CSA_to_ADC<2>" LOC = "R4" | IOSTANDARD = LVCMOS18 ;
NET "CSA_to_ADC<3>" LOC = "T7" | IOSTANDARD = LVCMOS18 ;
NET "CSA_to_ADC<4>" LOC = "R12" | IOSTANDARD = LVCMOS18 ;
NET "CSA_to_ADC<5>" LOC = "R16" | IOSTANDARD = LVCMOS18 ;
NET "CSA_to_ADC<6>" LOC = "M15" | IOSTANDARD = LVCMOS18 ;
NET "CSA_to_ADC<7>" LOC = "K14" | IOSTANDARD = LVCMOS18 ;
NET "CSB_to_ADC<0>" LOC = "L2" | IOSTANDARD = LVCMOS18 ;
NET "CSB_to_ADC<1>" LOC = "T1" | IOSTANDARD = LVCMOS18 ;
NET "CSB_to_ADC<2>" LOC = "R5" | IOSTANDARD = LVCMOS18 ;
NET "CSB_to_ADC<3>" LOC = "T8" | IOSTANDARD = LVCMOS18 ;
NET "CSB_to_ADC<4>" LOC = "R13" | IOSTANDARD = LVCMOS18 ;
NET "CSB_to_ADC<5>" LOC = "P16" | IOSTANDARD = LVCMOS18 ;
NET "CSB_to_ADC<6>" LOC = "L15" | IOSTANDARD = LVCMOS18 ;
NET "CSB_to_ADC<7>" LOC = "J14" | IOSTANDARD = LVCMOS18 ;
NET "SCK_from_FPGA" LOC = "A6" | IOSTANDARD = LVCMOS33 ;
NET "SCK_to_ADC<0>" LOC = "J1" | IOSTANDARD = LVCMOS18 ;
NET "SCK_to_ADC<1>" LOC = "M1" | IOSTANDARD = LVCMOS18 ;
NET "SCK_to_ADC<2>" LOC = "R2" | IOSTANDARD = LVCMOS18 ;
NET "SCK_to_ADC<3>" LOC = "T5" | IOSTANDARD = LVCMOS18 ;
NET "SCK_to_ADC<4>" LOC = "R8" | IOSTANDARD = LVCMOS18 ;
NET "SCK_to_ADC<5>" LOC = "R14" | IOSTANDARD = LVCMOS18 ;
NET "SCK_to_ADC<6>" LOC = "P15" | IOSTANDARD = LVCMOS18 ;
NET "SCK_to_ADC<7>" LOC = "L16" | IOSTANDARD = LVCMOS18 ;
NET "SCL_from_FPGA" LOC = "A9" | IOSTANDARD = LVCMOS33 ;
NET "SCL_to_I2C<0>" LOC = "A11" | IOSTANDARD = LVCMOS33 ;
NET "SCL_to_I2C<1>" LOC = "A13" | IOSTANDARD = LVCMOS33 ;
NET "SCL_to_I2C<2>" LOC = "A15" | IOSTANDARD = LVCMOS33 ;
NET "SCL_to_I2C<3>" LOC = "B16" | IOSTANDARD = LVCMOS33 ;
NET "SCL_to_I2C<4>" LOC = "E16" | IOSTANDARD = LVCMOS33 ;
NET "SCL_to_I2C<5>" LOC = "G16" | IOSTANDARD = LVCMOS33 ;
NET "SCL_to_I2C<6>" LOC = "B11" | IOSTANDARD = LVCMOS33 ;
NET "SCL_to_I2C<7>" LOC = "B13" | IOSTANDARD = LVCMOS33 ;
NET "SCL_to_I2C<8>" LOC = "B15" | IOSTANDARD = LVCMOS33 ;
#NET "SCL_to_I2C<9>" LOC = "E15" | IOSTANDARD = LVCMOS33 ;
#NET "SCL_to_I2C<10>" LOC = "G15" | IOSTANDARD = LVCMOS33 ;
#NET "SCL_to_I2C<11>" LOC = "B9" | IOSTANDARD = LVCMOS33 ;
NET "SCL_to_I2C<9>" LOC = "J3" | IOSTANDARD = LVCMOS18 ;
#NET "SCL_to_I2C<12>" LOC = "B7" | IOSTANDARD = LVCMOS33 ;
#NET "SCL_to_I2C<13>" LOC = "J3" | IOSTANDARD = LVCMOS18 ;
NET "SDA_I2C<0>" LOC = "A12" | IOSTANDARD = LVCMOS33 | PULLUP ;
NET "SDA_I2C<1>" LOC = "A14" | IOSTANDARD = LVCMOS33 | PULLUP ;
NET "SDA_I2C<2>" LOC = "A16" | IOSTANDARD = LVCMOS33 | PULLUP ;
NET "SDA_I2C<3>" LOC = "C16" | IOSTANDARD = LVCMOS33 | PULLUP ;
NET "SDA_I2C<4>" LOC = "F16" | IOSTANDARD = LVCMOS33 | PULLUP ;
NET "SDA_I2C<5>" LOC = "H16" | IOSTANDARD = LVCMOS33 | PULLUP ;
NET "SDA_I2C<6>" LOC = "B12" | IOSTANDARD = LVCMOS33 | PULLUP ;
NET "SDA_I2C<7>" LOC = "B14" | IOSTANDARD = LVCMOS33 | PULLUP ;
NET "SDA_I2C<8>" LOC = "D15" | IOSTANDARD = LVCMOS33 | PULLUP ;
#NET "SDA_I2C<9>" LOC = "F15" | IOSTANDARD = LVCMOS33 | PULLUP ;
#NET "SDA_I2C<10>" LOC = "H15" | IOSTANDARD = LVCMOS33 | PULLUP ;
#NET "SDA_I2C<11>" LOC = "B10" | IOSTANDARD = LVCMOS33 | PULLUP ;
NET "SDA_I2C<9>" LOC = "K3" | IOSTANDARD = LVCMOS18 | PULLUP ;
#NET "SDA_I2C<12>" LOC = "B8" | IOSTANDARD = LVCMOS33 | PULLUP ;
#NET "SDA_I2C<13>" LOC = "K3" | IOSTANDARD = LVCMOS18 | PULLUP ;
NET "SDA_in_to_FPGA" LOC = "A8" | IOSTANDARD = LVCMOS33 ;
NET "SDA_out_from_FPGA" LOC = "A7" | IOSTANDARD = LVCMOS33 ;
NET "SDI_to_ADC<0>" LOC = "J2" | IOSTANDARD = LVCMOS18 ;
NET "SDI_to_ADC<1>" LOC = "N1" | IOSTANDARD = LVCMOS18 ;
NET "SDI_to_ADC<2>" LOC = "R3" | IOSTANDARD = LVCMOS18 ;
NET "SDI_to_ADC<3>" LOC = "T6" | IOSTANDARD = LVCMOS18 ;
NET "SDI_to_ADC<4>" LOC = "R9" | IOSTANDARD = LVCMOS18 ;
NET "SDI_to_ADC<5>" LOC = "R15" | IOSTANDARD = LVCMOS18 ;
NET "SDI_to_ADC<6>" LOC = "N15" | IOSTANDARD = LVCMOS18 ;
NET "SDI_to_ADC<7>" LOC = "K16" | IOSTANDARD = LVCMOS18 ;
#
NET "SDI_to_FPGA" LOC = "A4" | IOSTANDARD = LVCMOS33 ;
NET "SDO_from_FPGA" LOC = "A5" | IOSTANDARD = LVCMOS33 ;
NET "SDOA_from_ADC<0>" LOC = "K1" | IOSTANDARD = LVCMOS18 ;
NET "SDOA_from_ADC<1>" LOC = "N2" | IOSTANDARD = LVCMOS18 ;
NET "SDOA_from_ADC<2>" LOC = "T3" | IOSTANDARD = LVCMOS18 ;
NET "SDOA_from_ADC<3>" LOC = "R6" | IOSTANDARD = LVCMOS18 ;
NET "SDOA_from_ADC<4>" LOC = "T10" | IOSTANDARD = LVCMOS18 ;
NET "SDOA_from_ADC<5>" LOC = "T15" | IOSTANDARD = LVCMOS18 ;
NET "SDOA_from_ADC<6>" LOC = "N16" | IOSTANDARD = LVCMOS18 ;
NET "SDOA_from_ADC<7>" LOC = "K15" | IOSTANDARD = LVCMOS18 ;
NET "SDOB_from_ADC<0>" LOC = "K2" | IOSTANDARD = LVCMOS18 ;
NET "SDOB_from_ADC<1>" LOC = "P1" | IOSTANDARD = LVCMOS18 ;
NET "SDOB_from_ADC<2>" LOC = "T4" | IOSTANDARD = LVCMOS18 ;
NET "SDOB_from_ADC<3>" LOC = "R7" | IOSTANDARD = LVCMOS18 ;
NET "SDOB_from_ADC<4>" LOC = "R10" | IOSTANDARD = LVCMOS18 ;
NET "SDOB_from_ADC<5>" LOC = "T16" | IOSTANDARD = LVCMOS18 ;
NET "SDOB_from_ADC<6>" LOC = "M16" | IOSTANDARD = LVCMOS18 ;
NET "SDOB_from_ADC<7>" LOC = "J15" | IOSTANDARD = LVCMOS18 ;
NET "SPI_CSN_FROM_FPGA" LOC = "H1" | IOSTANDARD = LVCMOS33 ;
NET "SFP_present<0>" LOC = "D2" |IOSTANDARD = LVCMOS33 ;
NET "SFP_tx_fault<0>" LOC = "F2" |IOSTANDARD = LVCMOS33 ;
NET "SFP_present<1>" LOC = "G3" |IOSTANDARD = LVCMOS33 ;
NET "SFP_tx_fault<1>" LOC = "H3" |IOSTANDARD = LVCMOS33 ;
NET "cpld_leds_o<1>" LOC = "H2" | IOSTANDARD = LVCMOS33;
NET "cpld_leds_o<0>" LOC = "E2" | IOSTANDARD = LVCMOS33 ;
# Can't use LEDs 2,3 -- put them in the wrong location :-(
#NET "cpld_leds_o<2>" LOC = "E1" | IOSTANDARD = LVCMOS33;
#NET "cpld_leds_o<3>" LOC = "F1" | IOSTANDARD = LVCMOS33;
# Acceptable locations include E8 , D4
NET "CLK_IN" LOC = "P5" | BUFG = CLK;
NET "temp_Alarm_i" LOC = "B2" | IOSTANDARD = LVCMOS33 ;
NET "temp_Alarm_Led_o" LOC = "C4" |IOSTANDARD = LVCMOS33 ;
NET "POR_i" LOC = "D3" | IOSTANDARD = LVCMOS33 ;
NET "PGood_from_FPGA_i" LOC = "B6" |IOSTANDARD = LVCMOS33 ;
NET "PGood_from_HDMI_i" LOC = "C7" |IOSTANDARD = LVCMOS33 | PULLUP ;
NET "FPGA_Power_Enable_o" LOC = "B3" |IOSTANDARD = LVCMOS33 ;
NET "PGood_o" LOC = "F3" |IOSTANDARD = LVCMOS33 ;
NET "PGood3v3_o" LOC = "B7" | IOSTANDARD = LVCMOS33 ;
NET "power_switch_high_on" LOC = "C3" |IOSTANDARD = LVCMOS33 | PULLUP;
NET "power_switch_high_off" LOC = "E3" |IOSTANDARD = LVCMOS33 | PULLUP ;
NET "fpga_en1" LOC = "B4" |IOSTANDARD = LVCMOS33 ;
NET "fpga_resin" LOC = "B5" |IOSTANDARD = LVCMOS33 ;
NET "GPIO<0>" LOC = "E14" |IOSTANDARD = LVCMOS33 ;
#NET "I2CEN_T" LOC = "E14" |IOSTANDARD = LVCMOS33 ;
NET "GPIO<1>" LOC = "F14" |IOSTANDARD = LVCMOS33 ;
NET "GPIO<2>" LOC = "G14" |IOSTANDARD = LVCMOS33 ;
NET "GPIO<3>" LOC = "H14" |IOSTANDARD = LVCMOS33 ;
NET "GPIO<4>" LOC = "B8" | IOSTANDARD = LVCMOS33 ;
NET "GPIO<5>" LOC = "F15" | IOSTANDARD = LVCMOS33 ;
NET "GPIO<6>" LOC = "H15" | IOSTANDARD = LVCMOS33 ;
NET "GPIO<7>" LOC = "B10" | IOSTANDARD = LVCMOS33 ;
NET "GPIO<8>" LOC = "E15" | IOSTANDARD = LVCMOS33 ;
NET "GPIO<9>" LOC = "G15" | IOSTANDARD = LVCMOS33 ;
#NET "GPIO<10>" LOC = "B9" | IOSTANDARD = LVCMOS33 ;
#PACE: Start of PACE Area Constraints
#PACE: Start of PACE Prohibit Constraints
#PACE: End of Constraints generated by PACE
firmware/CPLD/src/pc051c_cpld_v0-3.vhd
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......@@ -96,3 +96,7 @@ cpldfit -intstyle ise -p xc2c256-6-FT256 -ofmt vhdl -optimize density -htmlrpt -
XSLTProcess Multiplexer_build.xml
tsim -intstyle ise Multiplexer Multiplexer.nga
hprep6 -s IEEE1149 -i Multiplexer
XSLTProcess Multiplexer_build.xml
XSLTProcess Multiplexer_build.xml
XSLTProcess Multiplexer_build.xml
XSLTProcess Multiplexer_build.xml
firmware/pc051c_cpld/_ngo/netlist.lst
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/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/pc051c_cpld/Multiplexer.ngc 1500978186
/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/pc051c_cpld/pc051c_cpld.ngc 1518023977
OK
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/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/pc051c_cpld_v0-3/pc051c_cpld.ngc 1518089225
OK
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