Checking in CPLD simulation files before porting to Git

0c7f6de9 · David Cussans · f70504ae · 0c7f6de9 · 0c7f6de9 · 0c7f6de9
Commit 0c7f6de9 authored Jan 29, 2019 by David Cussans
57 changed files
--- a/firmware/CPLD/sim/compile_pc051c_cpld_debug_tb-0-3.sh
+++ b/firmware/CPLD/sim/compile_pc051c_cpld_debug_tb-0-3.sh
+#./configure /usr/local/ghdl
+#!/bin/bash -v
+ghdl -a SPItypes.vhd
+ghdl -a dummySPImaster.vhd
+ghdl -a dummySPIslave.vhd
+ghdl -a pc051c_cpld_debug_v0-3.vhd
+ghdl -a pc051c_cpld_debug_tb-0-3.vhd
+ghdl -e pc051c_cpld_tb
--- a/firmware/CPLD/sim_src/SPItypes.vhd
+++ b/firmware/CPLD/sim_src/SPItypes.vhd
+-- Data types for LTM9007 SPI tests.
+--
+-- 7 bit address. 8 bit data.
+--
+-- David Cussans, August 2017
+--
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+USE ieee.numeric_std.ALL;
+
+package SPITypes is
+
+  constant c_NUM_ADDRESS_BITS : integer := 7;
+  constant c_NUM_DATA_BITS : integer := 8;
+  constant c_NUM_ADCS : integer := 8;
+
+  type spiMasterTransaction is
+  record
+    r_adcNumber : integer range 0 to c_NUM_ADCS-1;
+    r_bank : integer range 0 to 1; -- 1 = bank-B , 0 = bank-A
+    r_testAddress : std_logic_vector(c_NUM_ADDRESS_BITS-1 downto 0);
+    r_testData : std_logic_vector(c_NUM_DATA_BITS-1 downto 0);
+    r_readWriteN : std_logic; -- 1 = read , 0 = write
+  end record;
+
+end SPITypes;
--- a/firmware/CPLD/sim_src/dummySPImaster.vhd
+++ b/firmware/CPLD/sim_src/dummySPImaster.vhd
+--
+-- Dummy SPI master for use with pc051 CPLD simulation
+--
+-- David Cussans, Aug 2017
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use STD.TEXTIO.all;
+use work.SPItypes.all;
+
+entity dummySPImaster is
+  generic (
+  g_SELECT_LENGTH : integer := 5;
+  g_SPI_CLOCK_PERIOD : time := 1000 ns
+);
+port (
+  trans_i : in spiMasterTransaction;
+  trans_o : out integer;
+  bus_select_o: out std_logic_vector(g_SELECT_LENGTH-1 downto 0);
+  sck_o : out std_logic;
+  sdo_o : out std_logic;
+  sdi_i : in std_logic;
+  csn_o : out std_logic
+);
+end dummySPImaster;
+
+
+architecture rtl of dummySPImaster is
+
+
+
+
+  begin
+
+  p_commandLoop: process
+
+    variable v_bus_select : std_logic_vector(bus_select_o'range);
+    variable v_word_length : natural := trans_i.r_testAddress'length +
+                                        trans_i.r_testData'length + 1;
+    variable v_bitsToWrite : std_logic_vector( v_word_length-1 downto 0);
+
+    --variable textLine : line;
+
+    begin
+
+      report "dummySPImaster: waiting for transaction" severity note;
+      wait on trans_i'transaction;
+
+      v_bus_select := std_logic_vector(
+                    to_unsigned(((trans_i.r_adcNumber*2) + trans_i.r_bank),
+                                    v_bus_select'length)) ;
+
+      v_bitsToWrite := trans_i.r_readWriteN &
+                      trans_i.r_testAddress &
+                      trans_i.r_testData ;
+
+      --report "dummySPIMaster: bits to write = " & to_string(v_bitsToWrite) severity note;
+      --hwrite(textLine);
+
+      -- Put test bench stimulus code here
+      bus_select_o <= std_logic_vector(to_unsigned(0, v_bus_select'length));
+      csn_o <= '1';
+      sck_o <= '0';
+      sdo_o <= '0';
+
+
+      report "dummySPImaster: Got transaction" severity note;
+
+      wait for g_SPI_CLOCK_PERIOD*2.5;
+      bus_select_o <= v_bus_select;
+      wait for g_SPI_CLOCK_PERIOD*2;
+      csn_o <= '0';
+      wait for g_SPI_CLOCK_PERIOD*2;
+
+      sck_o <= '0';
+      sdo_o <= '0';
+      wait for g_SPI_CLOCK_PERIOD/2;
+
+    -- Loop through bits to write
+    for bit in (v_word_length-1) downto 0 loop
+      sdo_o <= v_bitsToWrite(bit);
+      wait for g_SPI_CLOCK_PERIOD/2; -- data static for 1/2 clock period
+      sck_o <= '1';                  -- ... before clock goes high
+      wait for g_SPI_CLOCK_PERIOD/2;
+      sck_o <= '0';
+    end loop;
+
+    sdo_o <= '0';
+    sck_o <= '0';
+    wait for g_SPI_CLOCK_PERIOD*2;
+    csn_o <= '1';
+    wait for g_SPI_CLOCK_PERIOD*2;
+    bus_select_o <= std_logic_vector(to_unsigned(0, v_bus_select'length));
+    wait for g_SPI_CLOCK_PERIOD;
+
+    trans_o <= 0;
+
+    end process;
+
+end rtl;
--- a/firmware/CPLD/sim_src/dummySPIslave.vhd
+++ b/firmware/CPLD/sim_src/dummySPIslave.vhd
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use STD.TEXTIO.all;
+use work.SPItypes.all;
+
+entity dummySPIslave is
+  port (
+    RESET_in    : in  std_logic;
+    CLK_in      : in  std_logic;
+    SPI_CLK     : in std_logic;
+    SPI_SS      : in std_logic;
+    SPI_MOSI    : in  std_logic;
+    SPI_MISO    : out std_logic;
+    SPI_DONE    : out std_logic;
+    Address     : out std_logic_vector(6 downto 0);
+    Read_WriteB : out std_logic;
+    DataToTx    : in std_logic_vector(7 downto 0);
+    DataToTxLoad: in std_logic;
+    DataRxd     : out std_logic_vector(7 downto 0)
+    );
+end dummySPIslave;
+
+architecture Behavioral of dummySPIslave is
+
+    signal SCLK_latched, SCLK_old : std_logic;
+    signal SS_latched, SS_old : std_logic;
+    signal MOSI_latched: std_logic;
+    signal TxData : std_logic_vector(7 downto 0);
+    signal index: natural range 0 to 15;
+    signal RxdData : std_logic_vector(7 downto 0);
+    signal s_read_writeb : std_logic; -- set high if read, low if write
+    signal s_address : std_logic_vector( Address'range);
+    signal s_SPI_DONE : std_logic;
+
+    constant c_IDLE_DOUT := 'Z';
+
+begin
+
+ --
+ -- Sync process
+ --
+
+  process(CLK_in, RESET_in)
+
+ begin
+    if (RESET_in = '0') then
+      RxdData  <= ( others => '0');
+      index <= 15;
+      TxData  <= ( others => '0');
+      SCLK_old <= '0';
+      SCLK_latched <= '0';
+      SS_old <= '0';
+      SS_latched <= '0';
+      s_SPI_DONE <= '1';
+      MOSI_latched <= '0';
+      s_read_writeb <= '0';
+      s_address <= ( others => '0');
+
+    elsif( rising_edge(CLK_in) ) then
+
+      SCLK_latched <= SPI_CLK;
+      SCLK_old <= SCLK_latched;
+      SS_latched <= SPI_SS;
+      SS_old <= SS_latched;
+      MOSI_latched <= SPI_MOSI;
+
+      if(DataToTxLoad = '1') then
+          TxData <= DataToTx;
+      end if;
+
+      -- If CSN has fallen, then expect to read 16 bits.
+      if (SS_old = '1' and SS_latched = '0') then
+          index <= 15;
+          s_SPI_DONE <= '0';
+      end if;
+
+      if( SS_latched = '0' ) then
+
+        -- read data on rising edge
+        if(SCLK_old = '0' and SCLK_latched = '1') then
+
+          if (index = 15) then
+            s_read_writeb <= MOSI_latched;
+          elsif (index > 7) then
+            s_address <= s_address(5 downto 0) & MOSI_latched;
+          else
+            RxdData <= RxdData(6 downto 0) & MOSI_latched;
+          end if;
+
+          if(index = 0) then -- cycle ended
+              index <= 15;
+          elsif (s_SPI_DONE = '0') then
+            index <= index-1;
+          end if;
+
+        elsif(SCLK_old = '1' and SCLK_latched = '0') then
+            if( index = 15 ) then
+               s_SPI_DONE <= '1';
+            end if;
+
+        -- Handle Tx data
+        TxData <= TxData(6 downto 0) & '1';
+
+      end if; --(SCLK_old = '0' and SCLK_latched = '1')
+     end if; -- ( SS_latched = '0' )
+   end if; -- rising_edge(CLK_in)
+   end process;
+
+   --
+   -- Combinational assignments
+   --
+
+   Address <= s_address;
+   SPI_MISO <= TxData(7);
+   DataRxd <= RxdData;
+   Read_WriteB <= s_read_writeb;
+   SPI_DONE <= s_SPI_DONE;
+
+end Behavioral;
--- a/firmware/CPLD/sim_src/pc051c_cpld_debug_tb-0-3.vhd
+++ b/firmware/CPLD/sim_src/pc051c_cpld_debug_tb-0-3.vhd
+-- Testbench created online at:
+--   www.doulos.com/knowhow/perl/testbench_creation/
+-- Copyright Doulos Ltd
+-- SD, 03 November 2002
+
+library IEEE;
+use IEEE.Std_logic_1164.all;
+use IEEE.Numeric_Std.all;
+
+use work.SPITypes.all;
+
+entity pc051c_cpld_tb is
+generic (
+  g_NUM_SPI : natural := 8;
+  g_NUM_I2C : natural := 10;
+ g_NUM_SFP : natural := 2;
+ g_NUM_LEDS: natural := 2;
+ g_ENABLE_LEDS : boolean := TRUE
+ );
+end;
+
+architecture bench of pc051c_cpld_tb is
+
+
+  signal SCK_to_ADC: std_logic_vector(g_NUM_SPI-1 downto 0):= (others =>'0');
+  signal SDI_to_ADC: std_logic_vector(g_NUM_SPI-1 downto 0):= (others =>'0');
+  signal SDOA_from_ADC: std_logic_vector(g_NUM_SPI-1 downto 0) := (others =>'0');
+  signal SDOB_from_ADC: std_logic_vector(g_NUM_SPI-1 downto 0):= (others =>'0');
+  signal CSA_to_ADC: std_logic_vector(g_NUM_SPI-1 downto 0):= (others =>'0');
+  signal CSB_to_ADC: std_logic_vector(g_NUM_SPI-1 downto 0):= (others =>'0');
+  signal SDA_I2C: std_logic_vector(g_NUM_I2C-1 downto 0):= (others =>'0');
+  signal SCL_to_I2C: std_logic_vector(g_NUM_I2C-1 downto 0):= (others =>'0');
+  signal bus_select: std_logic_vector(4 downto 0):= (others =>'0');
+  signal SPI_CSN_FROM_FPGA: std_logic := '1';
+  signal SDI_to_FPGA: std_logic:= '0';
+  signal SDO_from_FPGA: std_logic:= '0';
+  signal SCK_from_FPGA: std_logic:= '0';
+  signal SDA_out_from_FPGA: std_logic:= '0';
+  signal SDA_in_to_FPGA: std_logic:= '0';
+  signal SCL_from_FPGA: std_logic:= '0';
+  signal SFP_present: std_logic_vector(g_NUM_SFP-1 downto 0):= (others =>'0');
+  signal SFP_LOS: std_logic_vector(g_NUM_SFP-1 downto 0):= (others =>'0');
+  signal SFP_tx_fault: std_logic_vector(g_NUM_SFP-1 downto 0):= (others =>'0');
+  signal clk_in: std_logic:= '0';
+  signal temp_Alarm_i: std_logic:= '0';
+  signal temp_Alarm_Led_o: std_logic:= '0';
+  signal cpld_leds_o: std_logic_vector(g_NUM_LEDS-1 downto 0):= (others =>'0');
+  signal POR_i: std_logic:= '0';
+  signal PGood_from_FPGA_i: std_logic:= '0';
+  signal PGood_from_HDMI_i: std_logic:= '0';
+  signal FPGA_Power_Enable_o: std_logic:= '0';
+  signal PGood3v3_o: std_logic:= '0';
+  signal PGood_o: std_logic:= '0';
+  signal power_switch_high_on: std_logic:= '0';
+  signal power_switch_high_off: std_logic:= '0';
+  signal fpga_en1: std_logic:= '0';
+  signal fpga_resin: std_logic:= '0';
+  signal gpio: std_logic_vector(9 downto 0) := (others =>'0');
+
+  signal s_transToMaster : spiMasterTransaction;
+  signal s_transFromMaster : integer;
+
+  constant cpld_clock_period: time := 20 ns;
+  constant sclk_clock_period: time := 1000 ns;
+  signal stop_the_clock: boolean;
+
+  constant testData : std_logic_vector(13 downto 0) := "11010101010111";
+  signal adc_to_test : integer := 3;
+
+  signal s_SPI_DONE   : std_logic;
+  signal s_Address     :  std_logic_vector(6 downto 0);
+  signal s_Read_WriteB : std_logic;
+  signal s_DataToTx    :  std_logic_vector(7 downto 0);
+  signal s_DataToTxLoad: std_logic;
+  signal s_DataRxd     :  std_logic_vector(7 downto 0);
+
+begin
+
+  -- Insert values for generic parameters !!
+  uut: entity work.pc051c_cpld(pc051c_cpld_arch) generic map
+                              ( g_NUM_SPI             => 8,
+                                 g_NUM_I2C             => 10,
+                                 g_NUM_SFP             => 2,
+                                 g_NUM_LEDS            => 2,
+                                 g_ENABLE_LEDS         => TRUE )
+                      port map ( SCK_to_ADC            => SCK_to_ADC,
+                                 SDI_to_ADC            => SDI_to_ADC,
+                                 SDOA_from_ADC         => SDOA_from_ADC,
+                                 SDOB_from_ADC         => SDOB_from_ADC,
+                                 CSA_to_ADC            => CSA_to_ADC,
+                                 CSB_to_ADC            => CSB_to_ADC,
+                                 SDA_I2C               => SDA_I2C,
+                                 SCL_to_I2C            => SCL_to_I2C,
+                                 bus_select            => bus_select,
+                                 SPI_CSN_FROM_FPGA     => SPI_CSN_FROM_FPGA,
+                                 SDI_to_FPGA           => SDI_to_FPGA,
+                                 SDO_from_FPGA         => SDO_from_FPGA,
+                                 SCK_from_FPGA         => SCK_from_FPGA,
+                                 SDA_out_from_FPGA     => SDA_out_from_FPGA,
+                                 SDA_in_to_FPGA        => SDA_in_to_FPGA,
+                                 SCL_from_FPGA         => SCL_from_FPGA,
+                                 SFP_present           => SFP_present,
+                                 SFP_LOS               => SFP_LOS,
+                                 SFP_tx_fault          => SFP_tx_fault,
+                                 clk_in                => clk_in,
+                                 temp_Alarm_i          => temp_Alarm_i,
+                                 temp_Alarm_Led_o      => temp_Alarm_Led_o,
+                                 cpld_leds_o           => cpld_leds_o,
+                                 POR_i                 => POR_i,
+                                 PGood_from_FPGA_i     => PGood_from_FPGA_i,
+                                 PGood_from_HDMI_i     => PGood_from_HDMI_i,
+                                 FPGA_Power_Enable_o   => FPGA_Power_Enable_o,
+                                 PGood3v3_o            => PGood3v3_o,
+                                 PGood_o               => PGood_o,
+                                 power_switch_high_on  => power_switch_high_on,
+                                 power_switch_high_off => power_switch_high_off,
+                                 fpga_en1              => fpga_en1,
+                                 fpga_resin            => fpga_resin,
+                                 gpio                  => gpio );
+
+  -- instantiate dummy SPI master
+  cmp_SPIMaster: entity work.dummySPImaster
+    generic map (
+      g_SELECT_LENGTH => bus_select'length,
+      g_SPI_CLOCK_PERIOD => 1000 ns
+      )
+    port map (
+      trans_i => s_transToMaster,
+      trans_o => s_transFromMaster,
+      bus_select_o => bus_select,
+      sck_o => SCK_from_FPGA,
+      sdo_o => SDO_from_FPGA,
+      sdi_i => SDI_to_FPGA,
+      csn_o => SPI_CSN_FROM_FPGA
+    );
+
+  -- instantiate a single SPI slave
+  cmp_SPISlave : entity work.dummySPIslave
+    port map(
+      RESET_in  => POR_i, -- active low
+      CLK_in    => clk_in,
+      SPI_CLK     => SCK_to_ADC(1),
+      SPI_SS      => CSA_to_ADC(1),
+      SPI_MOSI    => SDI_to_ADC(1),
+      SPI_MISO    => SDOA_from_ADC(1),
+      SPI_DONE    => s_SPI_DONE,
+      Address     => s_Address,
+      Read_WriteB => s_Read_WriteB ,
+      DataToTx    => s_DataToTx,
+      DataToTxLoad=> s_DataToTxLoad,
+      DataRxd     => s_DataRxd
+      );
+
+
+  stimulus: process
+
+    variable v_SPI_Master_transaction : spiMasterTransaction;
+  begin
+
+    -- Put initialisation code here
+
+    POR_i <= '0';
+    wait for 5 ns;
+    POR_i <= '1';
+    wait for 5 ns;
+
+    s_DataRxd <= "10100101";
+    s_DataToTxLoad <= '1';
+    wait for cpld_clock_period*2;
+    s_DataToTxLoad <= '0';
+
+    -- Put test bench stimulus code here
+
+    -- First fill v_SPI_Master_transaction variable
+    v_SPI_Master_transaction.r_adcNumber  := 1;
+    v_SPI_Master_transaction.r_bank := 0;
+    v_SPI_Master_transaction.r_testAddress := "1101011"; -- 0x6B
+    v_SPI_Master_transaction.r_testData := "11010011";   -- 0xD3
+    v_SPI_Master_transaction.r_readWriteN := '1';
+
+    -- Assigning to the s_transMaster signal will generate a transaction that triggers SPI master
+    s_transToMaster <= v_SPI_Master_transaction;
+
+    wait on s_transFromMaster'transaction;
+    report "pc051c_cpld_debug: Got transaction" severity note;
+
+    stop_the_clock <= true;
+    wait;
+  end process;
+
+  clocking: process
+  begin
+    while not stop_the_clock loop
+      clk_in <= '0', '1' after cpld_clock_period / 2;
+      wait for cpld_clock_period;
+    end loop;
+    wait;
+  end process;
+
+end;
--- a/firmware/CPLD/sim_src/pc051c_cpld_debug_v0-3.vhd
+++ b/firmware/CPLD/sim_src/pc051c_cpld_debug_v0-3.vhd
--- a/www/Docs/atlc/4.6
+++ b/www/Docs/atlc/4.6
--- a/www/Docs/atlc/50_ohm_1600umx3200um.E.bin
+++ b/www/Docs/atlc/50_ohm_1600umx3200um.E.bin
--- a/www/Docs/atlc/50_ohm_1600umx3200um.E.bmp
+++ b/www/Docs/atlc/50_ohm_1600umx3200um.E.bmp
--- a/www/Docs/atlc/50_ohm_1600umx3200um.Er.bin
+++ b/www/Docs/atlc/50_ohm_1600umx3200um.Er.bin
--- a/www/Docs/atlc/50_ohm_1600umx3200um.Er.bmp
+++ b/www/Docs/atlc/50_ohm_1600umx3200um.Er.bmp
--- a/www/Docs/atlc/50_ohm_1600umx3200um.Ex.bin
+++ b/www/Docs/atlc/50_ohm_1600umx3200um.Ex.bin
--- a/www/Docs/atlc/50_ohm_1600umx3200um.Ex.bmp
+++ b/www/Docs/atlc/50_ohm_1600umx3200um.Ex.bmp
--- a/www/Docs/atlc/50_ohm_1600umx3200um.Ey.bin
+++ b/www/Docs/atlc/50_ohm_1600umx3200um.Ey.bin
--- a/www/Docs/atlc/50_ohm_1600umx3200um.Ey.bmp
+++ b/www/Docs/atlc/50_ohm_1600umx3200um.Ey.bmp
--- a/www/Docs/atlc/50_ohm_1600umx3200um.U.bin
+++ b/www/Docs/atlc/50_ohm_1600umx3200um.U.bin
--- a/www/Docs/atlc/50_ohm_1600umx3200um.U.bmp
+++ b/www/Docs/atlc/50_ohm_1600umx3200um.U.bmp
--- a/www/Docs/atlc/50_ohm_1600umx3200um.V.bin
+++ b/www/Docs/atlc/50_ohm_1600umx3200um.V.bin
--- a/www/Docs/atlc/50_ohm_1600umx3200um.V.bmp
+++ b/www/Docs/atlc/50_ohm_1600umx3200um.V.bmp
--- a/www/Docs/atlc/50_ohm_1600umx3200um.bmp
+++ b/www/Docs/atlc/50_ohm_1600umx3200um.bmp
--- a/www/Docs/atlc/50_ohm_1600umx3200um.cmd
+++ b/www/Docs/atlc/50_ohm_1600umx3200um.cmd
+create_bmp_for_rect_in_rect 6400 3200 0  2917 35 6400 567 1600 1.0 4.6 50_ohm_1600umx3200um.bmp
--- a/www/Docs/atlc/50_ohm_1600umx3200um_01.log
+++ b/www/Docs/atlc/50_ohm_1600umx3200um_01.log
+50_ohm_1600umx3200um.bmp 2 Er=  2.80 Zo= 109.868 Ohms C=   50.8 pF/m L=  612.9 nH/m v= 1.793e+08 m/s v_f= 0.598 VERSION= 4.6.1
--- a/www/Docs/atlc/50_ohm_1600umx3200um_02.log
+++ b/www/Docs/atlc/50_ohm_1600umx3200um_02.log
+50_ohm_1600umx3200um.bmp 2 Er=  1.85 Zo= 135.010 Ohms C=   33.6 pF/m L=  612.9 nH/m v= 2.203e+08 m/s v_f= 0.735 VERSION= 4.6.1
--- a/www/Docs/atlc/50_ohm_1600umx3200um_03.log
+++ b/www/Docs/atlc/50_ohm_1600umx3200um_03.log
+50_ohm_1600umx3200um.bmp 2 Er=  2.82 Zo=  91.314 Ohms C=   61.3 pF/m L=  511.0 nH/m v= 1.787e+08 m/s v_f= 0.596 VERSION= 4.6.1
--- a/www/Docs/atlc/50_ohm_1600umx3200um_side_strips.E.bin
+++ b/www/Docs/atlc/50_ohm_1600umx3200um_side_strips.E.bin
--- a/www/Docs/atlc/50_ohm_1600umx3200um_side_strips.E.bmp
+++ b/www/Docs/atlc/50_ohm_1600umx3200um_side_strips.E.bmp
--- a/www/Docs/atlc/50_ohm_1600umx3200um_side_strips.Er.bin
+++ b/www/Docs/atlc/50_ohm_1600umx3200um_side_strips.Er.bin
--- a/www/Docs/atlc/50_ohm_1600umx3200um_side_strips.Er.bmp
+++ b/www/Docs/atlc/50_ohm_1600umx3200um_side_strips.Er.bmp
--- a/www/Docs/atlc/50_ohm_1600umx3200um_side_strips.Ex.bin
+++ b/www/Docs/atlc/50_ohm_1600umx3200um_side_strips.Ex.bin
--- a/www/Docs/atlc/50_ohm_1600umx3200um_side_strips.Ex.bmp
+++ b/www/Docs/atlc/50_ohm_1600umx3200um_side_strips.Ex.bmp
--- a/www/Docs/atlc/50_ohm_1600umx3200um_side_strips.Ey.bin
+++ b/www/Docs/atlc/50_ohm_1600umx3200um_side_strips.Ey.bin
--- a/www/Docs/atlc/50_ohm_1600umx3200um_side_strips.Ey.bmp
+++ b/www/Docs/atlc/50_ohm_1600umx3200um_side_strips.Ey.bmp
--- a/www/Docs/atlc/50_ohm_1600umx3200um_side_strips.U.bin
+++ b/www/Docs/atlc/50_ohm_1600umx3200um_side_strips.U.bin
--- a/www/Docs/atlc/50_ohm_1600umx3200um_side_strips.U.bmp
+++ b/www/Docs/atlc/50_ohm_1600umx3200um_side_strips.U.bmp
--- a/www/Docs/atlc/50_ohm_1600umx3200um_side_strips.V.bin
+++ b/www/Docs/atlc/50_ohm_1600umx3200um_side_strips.V.bin
--- a/www/Docs/atlc/50_ohm_1600umx3200um_side_strips.V.bmp
+++ b/www/Docs/atlc/50_ohm_1600umx3200um_side_strips.V.bmp
--- a/www/Docs/atlc/50_ohm_1600umx3200um_side_strips.bmp
+++ b/www/Docs/atlc/50_ohm_1600umx3200um_side_strips.bmp
--- a/www/Docs/atlc/50_ohm_1600umx3200um_side_strips_01.log
+++ b/www/Docs/atlc/50_ohm_1600umx3200um_side_strips_01.log
+50_ohm_1600umx3200um_side_strips.bmp 2 Er=  2.70 Zo=  78.562 Ohms C=   69.8 pF/m L=  430.7 nH/m v= 1.824e+08 m/s v_f= 0.609 VERSION= 4.6.1
--- a/www/Docs/atlc/50_ohm_6400umx6400um.E.bin
+++ b/www/Docs/atlc/50_ohm_6400umx6400um.E.bin
--- a/www/Docs/atlc/50_ohm_6400umx6400um.E.bmp
+++ b/www/Docs/atlc/50_ohm_6400umx6400um.E.bmp
--- a/www/Docs/atlc/50_ohm_6400umx6400um.Er.bin
+++ b/www/Docs/atlc/50_ohm_6400umx6400um.Er.bin
--- a/www/Docs/atlc/50_ohm_6400umx6400um.Er.bmp
+++ b/www/Docs/atlc/50_ohm_6400umx6400um.Er.bmp
--- a/www/Docs/atlc/50_ohm_6400umx6400um.Ex.bin
+++ b/www/Docs/atlc/50_ohm_6400umx6400um.Ex.bin
--- a/www/Docs/atlc/50_ohm_6400umx6400um.Ex.bmp
+++ b/www/Docs/atlc/50_ohm_6400umx6400um.Ex.bmp
--- a/www/Docs/atlc/50_ohm_6400umx6400um.Ey.bin
+++ b/www/Docs/atlc/50_ohm_6400umx6400um.Ey.bin
--- a/www/Docs/atlc/50_ohm_6400umx6400um.Ey.bmp
+++ b/www/Docs/atlc/50_ohm_6400umx6400um.Ey.bmp
--- a/www/Docs/atlc/50_ohm_6400umx6400um.U.bin
+++ b/www/Docs/atlc/50_ohm_6400umx6400um.U.bin
--- a/www/Docs/atlc/50_ohm_6400umx6400um.U.bmp
+++ b/www/Docs/atlc/50_ohm_6400umx6400um.U.bmp
--- a/www/Docs/atlc/50_ohm_6400umx6400um.V.bin
+++ b/www/Docs/atlc/50_ohm_6400umx6400um.V.bin
--- a/www/Docs/atlc/50_ohm_6400umx6400um.V.bmp
+++ b/www/Docs/atlc/50_ohm_6400umx6400um.V.bmp
--- a/www/Docs/atlc/50_ohm_6400umx6400um.bmp
+++ b/www/Docs/atlc/50_ohm_6400umx6400um.bmp
--- a/www/Docs/atlc/50_ohm_6400umx6400um_01.log
+++ b/www/Docs/atlc/50_ohm_6400umx6400um_01.log
+50_ohm_6400umx6400um.bmp 2 Er=  3.02 Zo=  97.655 Ohms C=   59.4 pF/m L=  566.2 nH/m v= 1.725e+08 m/s v_f= 0.575 VERSION= 4.6.1
--- a/www/Docs/atlc/drawing.pdf
+++ b/www/Docs/atlc/drawing.pdf
--- a/www/Docs/atlc/inkscape_drawing.svg
+++ b/www/Docs/atlc/inkscape_drawing.svg
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<!-- Created with Inkscape (http://www.inkscape.org/) -->
+
+<svg
+   xmlns:dc="http://purl.org/dc/elements/1.1/"
+   xmlns:cc="http://creativecommons.org/ns#"
+   xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#"
+   xmlns:svg="http://www.w3.org/2000/svg"
+   xmlns="http://www.w3.org/2000/svg"
+   xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd"
+   xmlns:inkscape="http://www.inkscape.org/namespaces/inkscape"
+   width="6400mm"
+   height="6400mm"
+   viewBox="0 0 22677.165 22677.165"
+   id="svg2"
+   version="1.1"
+   inkscape:version="0.91 r13725"
+   sodipodi:docname="inkscape_drawing.svg">
+  <defs
+     id="defs4" />
+  <sodipodi:namedview
+     id="base"
+     pagecolor="#ffffff"
+     bordercolor="#666666"
+     borderopacity="1.0"
+     inkscape:pageopacity="0.0"
+     inkscape:pageshadow="2"
+     inkscape:zoom="0.042553819"
+     inkscape:cx="11338.583"
+     inkscape:cy="11338.583"
+     inkscape:document-units="mm"
+     inkscape:current-layer="layer1"
+     showgrid="false"
+     inkscape:window-width="1920"
+     inkscape:window-height="1161"
+     inkscape:window-x="1920"
+     inkscape:window-y="0"
+     inkscape:window-maximized="1" />
+  <metadata
+     id="metadata7">
+    <rdf:RDF>
+      <cc:Work
+         rdf:about="">
+        <dc:format>image/svg+xml</dc:format>
+        <dc:type
+           rdf:resource="http://purl.org/dc/dcmitype/StillImage" />
+        <dc:title></dc:title>
+      </cc:Work>
+    </rdf:RDF>
+  </metadata>
+  <g
+     inkscape:label="Layer 1"
+     inkscape:groupmode="layer"
+     id="layer1"
+     transform="translate(0,21624.803)">
+    <rect
+       style="fill:#ac82ac;fill-opacity:1;stroke:none;stroke-width:70.86614227;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1;opacity:1"
+       id="rect4157"
+       width="22677.166"
+       height="7190.894"
+       x="23.499653"
+       y="-6138.5308"
+       rx="11.6168"
+       ry="11.6168" />
+    <rect
+       style="fill:#000000;stroke:#00ff00;stroke-opacity:1;fill-opacity:0;stroke-width:70.86613328;stroke-miterlimit:4;stroke-dasharray:none"
+       id="rect3355"
+       width="22630.166"
+       height="22630.166"
+       x="46.999306"
+       y="-21601.303"
+       rx="11.6168"
+       ry="11.6168" />
+    <path
+       style="fill:none;fill-rule:evenodd;stroke:#ff0000;stroke-width:124.01573325;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;stroke-miterlimit:4;stroke-dasharray:none"
+       d="m 8671.372,-6185.53 4370.936,-23.5"
+       id="path4159"
+       inkscape:connector-curvature="0" />
+  </g>
+</svg>
--- a/www/Docs/atlc/tmp.bmp
+++ b/www/Docs/atlc/tmp.bmp
--- a/www/Docs/read_masterpinout.pl
+++ b/www/Docs/read_masterpinout.pl
+#!/usr/bin/perl -w
+#
+use strict;
+use warnings;
+use Text::CSV;
+
+my $csv = Text::CSV->new({ sep_char => ',' });
+
+my $file = $ARGV[0] or die "Need to get CSV file on the command line\n";
+
+my $searchConnector = $ARGV[1];
+
+open(my $data, '<', $file) or die "Could not open '$file' $!\n";
+
+my $sigName = "";
+my $modulePin = 0;
+my $connectorName = "";
+my $baseBoardPin = "";
+
+while (my $line = <$data>) {
+
+  chomp $line;
+ 
+  if ($csv->parse($line)) {
+ 
+      my @fields = $csv->fields();
+
+      $sigName = $fields[1];
+      $modulePin = $fields[2];
+      $connectorName = $fields[3];
+      $baseBoardPin = $fields[4];
+
+      # print "$sigName, $modulePin, $connectorName, $baseBoardPin\n";
+      
+      if ($connectorName =~ /$searchConnector/) {
+
+	  if ($modulePin =~ /\d+/ ){
+	      print "$sigName, $modulePin, $connectorName, $baseBoardPin\n"; 
+	  }
+      }
+      
+  } else {
+      warn "Line could not be parsed: $line\n";
+  }
+}
--- a/www/Power_Cable_pin_out.html
+++ b/www/Power_Cable_pin_out.html