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EtherBone Core
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EtherBone Core
Commits
f19220ff
Commit
f19220ff
authored
Mar 20, 2018
by
Dimitris Lampridis
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Plain Diff
hdl: further cleanup of WB INT
parent
79a60811
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4 changed files
with
3 additions
and
7 deletions
+3
-7
eb_master_eth_tx.vhd
hdl/eb_master_core/eb_master_eth_tx.vhd
+0
-1
eb_master_top.vhd
hdl/eb_master_core/eb_master_top.vhd
+1
-1
ez_usb.vhd
hdl/eb_usb_core/ez_usb.vhd
+1
-3
ez_usb_fifos.vhd
hdl/eb_usb_core/ez_usb_fifos.vhd
+1
-2
No files found.
hdl/eb_master_core/eb_master_eth_tx.vhd
View file @
f19220ff
...
...
@@ -150,7 +150,6 @@ begin
r_dat_o
(
15
downto
0
)
=>
s_tx_dat
);
slave_o
.
ack
<=
r_ack
;
slave_o
.
int
<=
'0'
;
slave_o
.
rty
<=
'0'
;
slave_o
.
err
<=
'0'
;
slave_o
.
stall
<=
s_stall
;
...
...
hdl/eb_master_core/eb_master_top.vhd
View file @
f19220ff
...
...
@@ -343,7 +343,7 @@ begin
s_narrow_in
.
stb
<=
s_udp_we_o
;
s_narrow_in
.
dat
<=
s_udp_data_o
;
s_udp_valid_i
<=
s_udp_raw_o
and
s_udp_we_o
and
not
s_narrow_out
.
stall
;
s_narrow2framer
<=
(
'0'
,
'0'
,
'0'
,
'0'
,
'0'
,
(
others
=>
'0'
));
s_narrow2framer
<=
(
'0'
,
'0'
,
'0'
,
'0'
,
(
others
=>
'0'
));
else
s_udp_valid_i
<=
'0'
;
s_narrow_in
.
cyc
<=
s_framer2narrow
.
cyc
;
...
...
hdl/eb_usb_core/ez_usb.vhd
View file @
f19220ff
...
...
@@ -6,7 +6,7 @@
-- Author : Wesley W. Terpstra
-- Company : GSI
-- Created : 2013-04-04
-- Last update: 201
3-04-04
-- Last update: 201
8-03-20
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
...
...
@@ -251,7 +251,6 @@ begin
usb2uart_uart_o
.
err
<=
'0'
;
usb2uart_uart_o
.
rty
<=
'0'
;
usb2uart_uart_o
.
dat
<=
(
others
=>
'0'
);
usb2uart_uart_o
.
int
<=
'0'
;
-- this will drop bytes once buffers are full (no host connected)
U_RX
:
uart_async_rx
-- UART2USB
...
...
@@ -266,7 +265,6 @@ begin
uart2usb_uart_o
.
ack
<=
rx_ready
and
uart2usb_uart_i
.
cyc
and
uart2usb_uart_i
.
stb
;
uart2usb_uart_o
.
err
<=
'0'
;
uart2usb_uart_o
.
rty
<=
'0'
;
uart2usb_uart_o
.
int
<=
'0'
;
uart2usb_uart_o
.
dat
(
31
downto
8
)
<=
(
others
=>
'0'
);
uart2usb_uart_o
.
stall
<=
not
rx_ready
;
...
...
hdl/eb_usb_core/ez_usb_fifos.vhd
View file @
f19220ff
...
...
@@ -6,7 +6,7 @@
-- Author : Wesley W. Terpstra
-- Company : GSI
-- Created : 2013-03-26
-- Last update: 201
3-03-26
-- Last update: 201
8-03-20
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
...
...
@@ -151,7 +151,6 @@ begin
slave_o
(
i
)
.
ack
<=
ack
(
i
);
slave_o
(
i
)
.
err
<=
'0'
;
slave_o
(
i
)
.
rty
<=
'0'
;
slave_o
(
i
)
.
int
<=
'0'
;
slave_o
(
i
)
.
stall
<=
stall
(
i
);
slave_o
(
i
)
.
dat
(
word
'range
)
<=
dat4wb
(
i
);
slave_o
(
i
)
.
dat
(
c_wishbone_data_width
-1
downto
g_fifo_width
)
<=
(
others
=>
'0'
);
...
...
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