Commit bf105880 authored by Michael Reese's avatar Michael Reese

eb_fifo: make it work with ghdl

parent ba955bcb
...@@ -54,10 +54,13 @@ architecture rtl of eb_fifo is ...@@ -54,10 +54,13 @@ architecture rtl of eb_fifo is
signal w_idx : unsigned(c_depth downto 0); signal w_idx : unsigned(c_depth downto 0);
signal r_idx1 : unsigned(c_depth downto 0); signal r_idx1 : unsigned(c_depth downto 0);
signal w_idx1 : unsigned(c_depth downto 0); signal w_idx1 : unsigned(c_depth downto 0);
signal w_idx_ram : std_logic_vector(c_depth-1 downto 0);
signal r_idx1_ram : std_logic_vector(c_depth-1 downto 0);
constant c_low : unsigned(c_depth-1 downto 0) := (others => '0'); constant c_low : unsigned(c_depth-1 downto 0) := (others => '0');
constant c_high : unsigned(c_depth downto 0) := '1' & c_low; constant c_high : unsigned(c_depth downto 0) := '1' & c_low;
begin begin
ram : generic_simple_dpram ram : generic_simple_dpram
...@@ -71,13 +74,16 @@ begin ...@@ -71,13 +74,16 @@ begin
clka_i => clk_i, clka_i => clk_i,
bwea_i => (others => '1'), bwea_i => (others => '1'),
wea_i => w_push_i, wea_i => w_push_i,
aa_i => std_logic_vector(w_idx(c_depth-1 downto 0)), aa_i => w_idx_ram,
da_i => w_dat_i, da_i => w_dat_i,
clkb_i => clk_i, clkb_i => clk_i,
ab_i => std_logic_vector(r_idx1(c_depth-1 downto 0)), ab_i => r_idx1_ram,
qb_o => r_dat_o); qb_o => r_dat_o);
w_idx_ram <= std_logic_vector(w_idx(c_depth-1 downto 0));
r_idx1_ram <= std_logic_vector(r_idx1(c_depth-1 downto 0));
r_idx1 <= (r_idx+1) when r_pop_i ='1' else r_idx; r_idx1 <= (r_idx+1) when r_pop_i ='1' else r_idx;
w_idx1 <= (w_idx+1) when w_push_i='1' else w_idx; w_idx1 <= (w_idx+1) when w_push_i='1' else w_idx;
......
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