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EtherBone Core
Commit 35bca79a authored by A. Hahn's avatar A. Hahn
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eb_slave_core: removed wishbone int signals

parent d274abc3
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hdl/eb_slave_core/eb_cfg_fifo.vhd
View file @ 35bca79a
...@@ -33,12 +33,12 @@ entity eb_cfg_fifo is ...@@ -33,12 +33,12 @@ entity eb_cfg_fifo is
port( port(
clk_i : in std_logic; clk_i : in std_logic;
rstn_i : in std_logic; rstn_i : in std_logic;
errreg_i : in std_logic_vector(63 downto 0); errreg_i : in std_logic_vector(63 downto 0);
cfg_i : in t_wishbone_slave_in; cfg_i : in t_wishbone_slave_in;
cfg_o : out t_wishbone_slave_out; cfg_o : out t_wishbone_slave_out;
fsm_stb_i : in std_logic; fsm_stb_i : in std_logic;
fsm_adr_i : in t_wishbone_address; fsm_adr_i : in t_wishbone_address;
fsm_full_o : out std_logic; fsm_full_o : out std_logic;
...@@ -46,27 +46,27 @@ entity eb_cfg_fifo is ...@@ -46,27 +46,27 @@ entity eb_cfg_fifo is
mux_pop_i : in std_logic; mux_pop_i : in std_logic;
mux_dat_o : out t_wishbone_data; mux_dat_o : out t_wishbone_data;
mux_empty_o : out std_logic; mux_empty_o : out std_logic;
my_mac_o : out std_logic_vector(47 downto 0); my_mac_o : out std_logic_vector(47 downto 0);
my_ip_o : out std_logic_vector(31 downto 0); my_ip_o : out std_logic_vector(31 downto 0);
my_port_o : out std_logic_vector(15 downto 0)); my_port_o : out std_logic_vector(15 downto 0));
end eb_cfg_fifo; end eb_cfg_fifo;
architecture rtl of eb_cfg_fifo is architecture rtl of eb_cfg_fifo is
constant c_pad : std_logic_vector(31 downto 16) := (others => '0'); constant c_pad : std_logic_vector(31 downto 16) := (others => '0');
signal r_mac : std_logic_vector(6*8-1 downto 0); signal r_mac : std_logic_vector(6*8-1 downto 0);
signal r_ip : std_logic_vector(4*8-1 downto 0); signal r_ip : std_logic_vector(4*8-1 downto 0);
signal r_port : std_logic_vector(2*8-1 downto 0); signal r_port : std_logic_vector(2*8-1 downto 0);
signal s_fsm_adr : std_logic_vector(2 downto 0); signal s_fsm_adr : std_logic_vector(2 downto 0);
signal s_fifo_adr : std_logic_vector(2 downto 0); signal s_fifo_adr : std_logic_vector(2 downto 0);
signal s_fifo_empty : std_logic; signal s_fifo_empty : std_logic;
signal s_fifo_pop : std_logic; signal s_fifo_pop : std_logic;
signal r_cache_empty : std_logic; signal r_cache_empty : std_logic;
signal r_cache_adr : std_logic_vector(2 downto 0); signal r_cache_adr : std_logic_vector(2 downto 0);
impure function update(x : std_logic_vector) return std_logic_vector is impure function update(x : std_logic_vector) return std_logic_vector is
alias y : std_logic_vector(x'length-1 downto 0) is x; alias y : std_logic_vector(x'length-1 downto 0) is x;
variable o : std_logic_vector(x'length-1 downto 0); variable o : std_logic_vector(x'length-1 downto 0);
...@@ -78,13 +78,12 @@ architecture rtl of eb_cfg_fifo is ...@@ -78,13 +78,12 @@ architecture rtl of eb_cfg_fifo is
o(i*8+7 downto i*8) := y(i*8+7 downto i*8); o(i*8+7 downto i*8) := y(i*8+7 downto i*8);
end if; end if;
end loop; end loop;
return o; return o;
end update; end update;
begin begin
cfg_o.int <= '0';
cfg_o.err <= '0'; cfg_o.err <= '0';
cfg_o.rty <= '0'; cfg_o.rty <= '0';
cfg_o.stall <= '0'; cfg_o.stall <= '0';
...@@ -95,7 +94,7 @@ begin ...@@ -95,7 +94,7 @@ begin
r_mac <= x"D15EA5EDBEEF"; r_mac <= x"D15EA5EDBEEF";
r_ip <= x"C0A80064"; r_ip <= x"C0A80064";
r_port <= x"EBD0"; r_port <= x"EBD0";
cfg_o.ack <= '0'; cfg_o.ack <= '0';
cfg_o.dat <= (others => '0'); cfg_o.dat <= (others => '0');
elsif rising_edge(clk_i) then elsif rising_edge(clk_i) then
...@@ -108,9 +107,9 @@ begin ...@@ -108,9 +107,9 @@ begin
when others => null; when others => null;
end case; end case;
end if; end if;
cfg_o.ack <= cfg_i.cyc and cfg_i.stb; cfg_o.ack <= cfg_i.cyc and cfg_i.stb;
case to_integer(unsigned(cfg_i.adr(4 downto 2))) is case to_integer(unsigned(cfg_i.adr(4 downto 2))) is
when 0 => cfg_o.dat <= errreg_i(63 downto 32); when 0 => cfg_o.dat <= errreg_i(63 downto 32);
when 1 => cfg_o.dat <= errreg_i(31 downto 0); when 1 => cfg_o.dat <= errreg_i(31 downto 0);
...@@ -121,13 +120,13 @@ begin ...@@ -121,13 +120,13 @@ begin
when 6 => cfg_o.dat <= r_ip; when 6 => cfg_o.dat <= r_ip;
when others => cfg_o.dat <= c_pad & r_port; when others => cfg_o.dat <= c_pad & r_port;
end case; end case;
end if; end if;
end process; end process;
-- Discard writes. -- Discard writes.
s_fsm_adr <= fsm_adr_i(4 downto 2); s_fsm_adr <= fsm_adr_i(4 downto 2);
fifo : eb_fifo fifo : eb_fifo
generic map( generic map(
g_width => 3, g_width => 3,
...@@ -141,9 +140,9 @@ begin ...@@ -141,9 +140,9 @@ begin
r_empty_o => s_fifo_empty, r_empty_o => s_fifo_empty,
r_pop_i => s_fifo_pop, r_pop_i => s_fifo_pop,
r_dat_o => s_fifo_adr); r_dat_o => s_fifo_adr);
s_fifo_pop <= not s_fifo_empty and (r_cache_empty or mux_pop_i); s_fifo_pop <= not s_fifo_empty and (r_cache_empty or mux_pop_i);
cache : process(rstn_i, clk_i) is cache : process(rstn_i, clk_i) is
begin begin
if rstn_i = '0' then if rstn_i = '0' then
...@@ -156,11 +155,11 @@ begin ...@@ -156,11 +155,11 @@ begin
end if; end if;
end if; end if;
end process; end process;
mux_empty_o <= r_cache_empty; mux_empty_o <= r_cache_empty;
with r_cache_adr select with r_cache_adr select
mux_dat_o <= mux_dat_o <=
errreg_i(63 downto 32) when "000", errreg_i(63 downto 32) when "000",
errreg_i(31 downto 0) when "001", errreg_i(31 downto 0) when "001",
x"00000000" when "010", x"00000000" when "010",
...@@ -169,7 +168,7 @@ begin ...@@ -169,7 +168,7 @@ begin
r_mac(31 downto 0) when "101", r_mac(31 downto 0) when "101",
r_ip when "110", r_ip when "110",
c_pad & r_port when others; c_pad & r_port when others;
my_mac_o <= r_mac; my_mac_o <= r_mac;
my_ip_o <= r_ip; my_ip_o <= r_ip;
my_port_o <= r_port; my_port_o <= r_port;
......
hdl/eb_slave_core/eb_eth_tx.vhd
View file @ 35bca79a
...@@ -34,11 +34,11 @@ end eb_eth_tx; ...@@ -34,11 +34,11 @@ end eb_eth_tx;
architecture rtl of eb_eth_tx is architecture rtl of eb_eth_tx is
type t_state is (S_WRF_STATUS, S_ETHERNET, S_IP, S_UDP, S_DONE, S_WAIT, S_PAYLOAD, S_RUNT, S_LOWER, S_SKIP, S_PUSH); type t_state is (S_WRF_STATUS, S_ETHERNET, S_IP, S_UDP, S_DONE, S_WAIT, S_PAYLOAD, S_RUNT, S_LOWER, S_SKIP, S_PUSH);
type t_sum_state is (S_CONST, S_DST_HI, S_DST_LO, S_SRC_HI, S_SRC_LO, S_LENGTH, S_DONE); type t_sum_state is (S_CONST, S_DST_HI, S_DST_LO, S_SRC_HI, S_SRC_LO, S_LENGTH, S_DONE);
signal r_state : t_state; signal r_state : t_state;
signal r_staten : t_state; signal r_staten : t_state;
signal r_count : unsigned(4 downto 0); signal r_count : unsigned(4 downto 0);
signal r_ready : std_logic; signal r_ready : std_logic;
signal r_mac : std_logic_vector(47 downto 0); signal r_mac : std_logic_vector(47 downto 0);
signal r_ip : std_logic_vector(31 downto 0); signal r_ip : std_logic_vector(31 downto 0);
...@@ -49,7 +49,7 @@ architecture rtl of eb_eth_tx is ...@@ -49,7 +49,7 @@ architecture rtl of eb_eth_tx is
signal r_shift : std_logic_vector(c_ip_len*8-1 downto 0); signal r_shift : std_logic_vector(c_ip_len*8-1 downto 0);
signal r_ack : std_logic; signal r_ack : std_logic;
signal s_stall : std_logic; signal s_stall : std_logic;
signal s_buf_stb : std_logic; signal s_buf_stb : std_logic;
signal s_buf_full : std_logic; signal s_buf_full : std_logic;
signal s_buf_push : std_logic; signal s_buf_push : std_logic;
...@@ -58,22 +58,22 @@ architecture rtl of eb_eth_tx is ...@@ -58,22 +58,22 @@ architecture rtl of eb_eth_tx is
signal s_buf_cyc : std_logic; signal s_buf_cyc : std_logic;
signal s_buf_data : std_logic_vector(15 downto 0); signal s_buf_data : std_logic_vector(15 downto 0);
signal r_buf_typ : std_logic; signal r_buf_typ : std_logic;
signal r_tx_cyc : std_logic; signal r_tx_cyc : std_logic;
signal s_tx_empty : std_logic; signal s_tx_empty : std_logic;
signal s_tx_pop : std_logic; signal s_tx_pop : std_logic;
signal s_tx_cyc : std_logic; signal s_tx_cyc : std_logic;
signal s_tx_typ : std_logic; signal s_tx_typ : std_logic;
signal s_tx_dat : std_logic_vector(15 downto 0); signal s_tx_dat : std_logic_vector(15 downto 0);
signal r_sum_state : t_sum_state; signal r_sum_state : t_sum_state;
signal r_sum_en : std_logic; signal r_sum_en : std_logic;
signal r_sum_data : std_logic_vector(15 downto 0); signal r_sum_data : std_logic_vector(15 downto 0);
signal s_sum_done : std_logic_vector(15 downto 0); signal s_sum_done : std_logic_vector(15 downto 0);
constant c_hdr_len : natural := c_ip_len; constant c_hdr_len : natural := c_ip_len;
constant c_runt_min : natural := 46 - c_ip_len; constant c_runt_min : natural := 46 - c_ip_len;
function f_send_eth(dst, src : std_logic_vector(47 downto 0)) return std_logic_vector is function f_send_eth(dst, src : std_logic_vector(47 downto 0)) return std_logic_vector is
variable o : std_logic_vector(c_hdr_len*8-1 downto 0) := (others => '-'); variable o : std_logic_vector(c_hdr_len*8-1 downto 0) := (others => '-');
variable eth : t_eth_hdr := c_eth_init; variable eth : t_eth_hdr := c_eth_init;
...@@ -83,7 +83,7 @@ architecture rtl of eb_eth_tx is ...@@ -83,7 +83,7 @@ architecture rtl of eb_eth_tx is
o(o'left downto (c_hdr_len-c_eth_len)*8) := f_format_eth(eth); o(o'left downto (c_hdr_len-c_eth_len)*8) := f_format_eth(eth);
return o; return o;
end function; end function;
function f_send_ip(dst, src : std_logic_vector(31 downto 0); len : unsigned(15 downto 0); sum : std_logic_vector(15 downto 0)) return std_logic_vector is function f_send_ip(dst, src : std_logic_vector(31 downto 0); len : unsigned(15 downto 0); sum : std_logic_vector(15 downto 0)) return std_logic_vector is
variable o : std_logic_vector(c_hdr_len*8-1 downto 0) := (others => '-'); variable o : std_logic_vector(c_hdr_len*8-1 downto 0) := (others => '-');
variable ip : t_ip_hdr := c_ip_init; variable ip : t_ip_hdr := c_ip_init;
...@@ -95,7 +95,7 @@ architecture rtl of eb_eth_tx is ...@@ -95,7 +95,7 @@ architecture rtl of eb_eth_tx is
o(o'left downto (c_hdr_len-c_ip_len)*8) := f_format_ip(ip); o(o'left downto (c_hdr_len-c_ip_len)*8) := f_format_ip(ip);
return o; return o;
end function; end function;
function f_send_udp(dst, src : std_logic_vector(15 downto 0); len : unsigned(15 downto 0)) return std_logic_vector is function f_send_udp(dst, src : std_logic_vector(15 downto 0); len : unsigned(15 downto 0)) return std_logic_vector is
variable o : std_logic_vector(c_hdr_len*8-1 downto 0) := (others => '-'); variable o : std_logic_vector(c_hdr_len*8-1 downto 0) := (others => '-');
variable udp : t_udp_hdr := c_udp_init; variable udp : t_udp_hdr := c_udp_init;
...@@ -106,12 +106,12 @@ architecture rtl of eb_eth_tx is ...@@ -106,12 +106,12 @@ architecture rtl of eb_eth_tx is
o(o'left downto (c_hdr_len-c_udp_len)*8) := f_format_udp(udp); o(o'left downto (c_hdr_len-c_udp_len)*8) := f_format_udp(udp);
return o; return o;
end function; end function;
function f_step(x : natural) return unsigned is function f_step(x : natural) return unsigned is
begin begin
return to_unsigned(x/2 - 1, 5); return to_unsigned(x/2 - 1, 5);
end function; end function;
begin begin
tx : eb_commit_fifo tx : eb_commit_fifo
...@@ -133,16 +133,15 @@ begin ...@@ -133,16 +133,15 @@ begin
r_dat_o(17) => s_tx_cyc, r_dat_o(17) => s_tx_cyc,
r_dat_o(16) => s_tx_typ, r_dat_o(16) => s_tx_typ,
r_dat_o(15 downto 0) => s_tx_dat); r_dat_o(15 downto 0) => s_tx_dat);
slave_o.ack <= r_ack; slave_o.ack <= r_ack;
slave_o.int <= '0';
slave_o.rty <= '0'; slave_o.rty <= '0';
slave_o.err <= '0'; slave_o.err <= '0';
slave_o.stall <= s_stall; slave_o.stall <= s_stall;
slave_o.dat <= (others => '0'); slave_o.dat <= (others => '0');
stall_o <= r_ready; -- already have params stall_o <= r_ready; -- already have params
s_stall <= s_buf_full when r_state=S_PAYLOAD else '1'; s_stall <= s_buf_full when r_state=S_PAYLOAD else '1';
skip_stall_o <= '0' when r_state=S_SKIP else '1'; skip_stall_o <= '0' when r_state=S_SKIP else '1';
s_buf_stb <= (slave_i.cyc and slave_i.stb) when r_state=S_PAYLOAD else r_hdr_stb; s_buf_stb <= (slave_i.cyc and slave_i.stb) when r_state=S_PAYLOAD else r_hdr_stb;
...@@ -151,7 +150,7 @@ begin ...@@ -151,7 +150,7 @@ begin
s_buf_commit <= '1' when r_state=S_LOWER else '0'; s_buf_commit <= '1' when r_state=S_LOWER else '0';
s_buf_cyc <= '0' when r_state=S_LOWER else '1'; s_buf_cyc <= '0' when r_state=S_LOWER else '1';
s_buf_data <= slave_i.dat(15 downto 0) when r_state=S_PAYLOAD else r_shift(r_shift'left downto r_shift'left-15); s_buf_data <= slave_i.dat(15 downto 0) when r_state=S_PAYLOAD else r_shift(r_shift'left downto r_shift'left-15);
hdr : process(clk_i, rst_n_i) is hdr : process(clk_i, rst_n_i) is
begin begin
if rst_n_i = '0' then if rst_n_i = '0' then
...@@ -169,11 +168,11 @@ begin ...@@ -169,11 +168,11 @@ begin
r_tx_cyc <= '0'; r_tx_cyc <= '0';
elsif rising_edge(clk_i) then elsif rising_edge(clk_i) then
r_ack <= slave_i.cyc and slave_i.stb and not s_stall; r_ack <= slave_i.cyc and slave_i.stb and not s_stall;
if s_tx_empty = '0' then if s_tx_empty = '0' then
r_tx_cyc <= s_tx_cyc; r_tx_cyc <= s_tx_cyc;
end if; end if;
if stb_i = '1' and r_ready = '0' then if stb_i = '1' and r_ready = '0' then
r_mac <= mac_i; r_mac <= mac_i;
r_ip <= ip_i; r_ip <= ip_i;
...@@ -181,7 +180,7 @@ begin ...@@ -181,7 +180,7 @@ begin
r_length <= length_i; r_length <= length_i;
r_ready <= '1'; r_ready <= '1';
end if; end if;
case r_state is case r_state is
when S_WRF_STATUS => when S_WRF_STATUS =>
if r_ready = '1' then if r_ready = '1' then
...@@ -190,7 +189,7 @@ begin ...@@ -190,7 +189,7 @@ begin
r_shift <= (others => '0'); r_shift <= (others => '0');
r_state <= S_ETHERNET; r_state <= S_ETHERNET;
end if; end if;
when S_ETHERNET => when S_ETHERNET =>
if s_buf_full = '0' then if s_buf_full = '0' then
r_buf_typ <= '0'; r_buf_typ <= '0';
...@@ -199,7 +198,7 @@ begin ...@@ -199,7 +198,7 @@ begin
r_staten <= S_IP; r_staten <= S_IP;
r_state <= S_PUSH; r_state <= S_PUSH;
end if; end if;
when S_IP => when S_IP =>
if s_buf_full = '0' then if s_buf_full = '0' then
r_shift <= f_send_ip(r_ip, my_ip_i, r_length, s_sum_done); r_shift <= f_send_ip(r_ip, my_ip_i, r_length, s_sum_done);
...@@ -207,7 +206,7 @@ begin ...@@ -207,7 +206,7 @@ begin
r_staten <= S_UDP; r_staten <= S_UDP;
r_state <= S_PUSH; r_state <= S_PUSH;
end if; end if;
when S_UDP => when S_UDP =>
if s_buf_full = '0' then if s_buf_full = '0' then
r_shift <= f_send_udp(r_port, my_port_i, r_length); r_shift <= f_send_udp(r_port, my_port_i, r_length);
...@@ -215,15 +214,15 @@ begin ...@@ -215,15 +214,15 @@ begin
r_staten <= S_DONE; r_staten <= S_DONE;
r_state <= S_PUSH; r_state <= S_PUSH;
end if; end if;
when S_DONE => when S_DONE =>
if s_buf_full = '0' then if s_buf_full = '0' then
r_ready <= '0'; -- can latch next header params r_ready <= '0'; -- can latch next header params
r_hdr_stb <= '0'; -- nothing more from the header side of things r_hdr_stb <= '0'; -- nothing more from the header side of things
-- After payload, may need to add runt padding -- After payload, may need to add runt padding
r_shift <= (others => '0'); r_shift <= (others => '0');
if r_length < c_runt_min then if r_length < c_runt_min then
r_staten <= S_RUNT; r_staten <= S_RUNT;
r_count <= f_step(c_runt_min - to_integer(r_length)); r_count <= f_step(c_runt_min - to_integer(r_length));
...@@ -231,7 +230,7 @@ begin ...@@ -231,7 +230,7 @@ begin
r_staten <= S_LOWER; r_staten <= S_LOWER;
r_count <= (others => '-'); r_count <= (others => '-');
end if; end if;
-- Make sure we don't skip the payload! -- Make sure we don't skip the payload!
if slave_i.cyc = '1' then if slave_i.cyc = '1' then
r_state <= S_PAYLOAD; r_state <= S_PAYLOAD;
...@@ -241,45 +240,45 @@ begin ...@@ -241,45 +240,45 @@ begin
r_state <= S_WAIT; r_state <= S_WAIT;
end if; end if;
end if; end if;
when S_WAIT => when S_WAIT =>
if slave_i.cyc = '1' then if slave_i.cyc = '1' then
r_state <= S_PAYLOAD; r_state <= S_PAYLOAD;
elsif skip_stb_i = '1' then elsif skip_stb_i = '1' then
r_state <= S_SKIP; r_state <= S_SKIP;
end if; end if;
when S_PAYLOAD => when S_PAYLOAD =>
if slave_i.cyc = '0' then if slave_i.cyc = '0' then
r_hdr_stb <= '1'; r_hdr_stb <= '1';
r_state <= r_staten; r_state <= r_staten;
end if; end if;
when S_RUNT => when S_RUNT =>
if s_buf_full = '0' then if s_buf_full = '0' then
r_state <= S_PUSH; r_state <= S_PUSH;
r_staten <= S_LOWER; r_staten <= S_LOWER;
end if; end if;
when S_LOWER => when S_LOWER =>
if s_buf_full = '0' then if s_buf_full = '0' then
r_hdr_stb <= '0'; r_hdr_stb <= '0';
r_state <= S_WRF_STATUS; r_state <= S_WRF_STATUS;
end if; end if;
when S_SKIP => when S_SKIP =>
r_state <= S_WRF_STATUS; r_state <= S_WRF_STATUS;
when S_PUSH => when S_PUSH =>
if s_buf_full = '0' then if s_buf_full = '0' then
r_count <= r_count - 1; r_count <= r_count - 1;
r_shift <= r_shift(r_shift'left-16 downto 0) & x"0000"; r_shift <= r_shift(r_shift'left-16 downto 0) & x"0000";
if r_count = to_unsigned(1, r_count'length) then if r_count = to_unsigned(1, r_count'length) then
r_state <= r_staten; r_state <= r_staten;
end if; end if;
end if; end if;
end case; end case;
end if; end if;
end process; end process;
...@@ -290,9 +289,9 @@ begin ...@@ -290,9 +289,9 @@ begin
src_o.we <= '1'; src_o.we <= '1';
src_o.sel <= "11"; src_o.sel <= "11";
src_o.dat <= s_tx_dat; src_o.dat <= s_tx_dat;
s_tx_pop <= not s_tx_empty and not (s_tx_cyc and src_i.stall); s_tx_pop <= not s_tx_empty and not (s_tx_cyc and src_i.stall);
sum : eb_checksum sum : eb_checksum
port map( port map(
clk_i => clk_i, clk_i => clk_i,
...@@ -301,7 +300,7 @@ begin ...@@ -301,7 +300,7 @@ begin
data_i => r_sum_data, data_i => r_sum_data,
done_o => open, done_o => open,
sum_o => s_sum_done); sum_o => s_sum_done);
sum_header : process(clk_i, rst_n_i) is sum_header : process(clk_i, rst_n_i) is
begin begin
if rst_n_i = '0' then if rst_n_i = '0' then
...@@ -309,7 +308,7 @@ begin ...@@ -309,7 +308,7 @@ begin
r_sum_en <= '0'; r_sum_en <= '0';
r_sum_data <= (others => '0'); r_sum_data <= (others => '0');
elsif rising_edge(clk_i) then elsif rising_edge(clk_i) then
case r_sum_state is case r_sum_state is
when S_CONST => when S_CONST =>
r_sum_data <= f_checksum(f_format_ip(c_ip_init)); r_sum_data <= f_checksum(f_format_ip(c_ip_init));
...@@ -317,7 +316,7 @@ begin ...@@ -317,7 +316,7 @@ begin
r_sum_en <= '1'; r_sum_en <= '1';
r_sum_state <= S_DST_HI; r_sum_state <= S_DST_HI;
end if; end if;
when S_DST_HI => r_sum_state <= S_DST_LO; r_sum_data <= r_ip(31 downto 16); when S_DST_HI => r_sum_state <= S_DST_LO; r_sum_data <= r_ip(31 downto 16);
when S_DST_LO => r_sum_state <= S_SRC_HI; r_sum_data <= r_ip(15 downto 0); when S_DST_LO => r_sum_state <= S_SRC_HI; r_sum_data <= r_ip(15 downto 0);
when S_SRC_HI => r_sum_state <= S_SRC_LO; r_sum_data <= my_ip_i(31 downto 16); when S_SRC_HI => r_sum_state <= S_SRC_LO; r_sum_data <= my_ip_i(31 downto 16);
...@@ -325,8 +324,8 @@ begin ...@@ -325,8 +324,8 @@ begin
when S_LENGTH => r_sum_state <= S_DONE; r_sum_data <= std_logic_vector(r_length+20); when S_LENGTH => r_sum_state <= S_DONE; r_sum_data <= std_logic_vector(r_length+20);
when S_DONE => r_sum_state <= S_CONST; r_sum_en <= '0'; when S_DONE => r_sum_state <= S_CONST; r_sum_en <= '0';
end case; end case;
end if; end if;
end process; end process;
end rtl; end rtl;
hdl/eb_slave_core/eb_slave_top.vhd
View file @ 35bca79a
...@@ -39,7 +39,7 @@ entity eb_slave_top is ...@@ -39,7 +39,7 @@ entity eb_slave_top is
EB_RX_o : out t_wishbone_slave_out; --! Streaming WB sink flow control to RX transport protocol block EB_RX_o : out t_wishbone_slave_out; --! Streaming WB sink flow control to RX transport protocol block
EB_TX_i : in t_wishbone_master_in; --! Streaming WB src flow control from TX transport protocol block EB_TX_i : in t_wishbone_master_in; --! Streaming WB src flow control from TX transport protocol block
EB_TX_o : out t_wishbone_master_out; --! Streaming WB src to TX transport protocol block EB_TX_o : out t_wishbone_master_out; --! Streaming WB src to TX transport protocol block
skip_stb_o : out std_logic; --! Does a packet get discarded? skip_stb_o : out std_logic; --! Does a packet get discarded?
skip_stall_i: in std_logic; skip_stall_i: in std_logic;
...@@ -47,7 +47,7 @@ entity eb_slave_top is ...@@ -47,7 +47,7 @@ entity eb_slave_top is
WB_config_o : out t_wishbone_slave_out; --! WB V4 interface to WB interconnect/device(s) WB_config_o : out t_wishbone_slave_out; --! WB V4 interface to WB interconnect/device(s)
WB_master_i : in t_wishbone_master_in; --! WB V4 interface to WB interconnect/device(s) WB_master_i : in t_wishbone_master_in; --! WB V4 interface to WB interconnect/device(s)
WB_master_o : out t_wishbone_master_out; --! WB V4 interface to WB interconnect/device(s) WB_master_o : out t_wishbone_master_out; --! WB V4 interface to WB interconnect/device(s)
my_mac_o : out std_logic_vector(47 downto 0); my_mac_o : out std_logic_vector(47 downto 0);
my_ip_o : out std_logic_vector(31 downto 0); my_ip_o : out std_logic_vector(31 downto 0);
my_port_o : out std_logic_vector(15 downto 0)); my_port_o : out std_logic_vector(15 downto 0));
...@@ -55,10 +55,10 @@ end eb_slave_top; ...@@ -55,10 +55,10 @@ end eb_slave_top;
architecture rtl of eb_slave_top is architecture rtl of eb_slave_top is
signal rstn_i : std_logic; signal rstn_i : std_logic;
signal errreg : std_logic_vector(63 downto 0); signal errreg : std_logic_vector(63 downto 0);
signal rx_stall : std_logic; signal rx_stall : std_logic;
signal fsm_tag_stb : std_logic; signal fsm_tag_stb : std_logic;
signal fsm_tag_dat : t_tag; signal fsm_tag_dat : t_tag;
signal tag_fsm_full : std_logic; signal tag_fsm_full : std_logic;
...@@ -71,7 +71,7 @@ architecture rtl of eb_slave_top is ...@@ -71,7 +71,7 @@ architecture rtl of eb_slave_top is
signal fsm_wbm_stb : std_logic; signal fsm_wbm_stb : std_logic;
signal wbm_fsm_full : std_logic; signal wbm_fsm_full : std_logic;
signal wbm_fsm_busy : std_logic; signal wbm_fsm_busy : std_logic;
signal mux_tag_pop : std_logic; signal mux_tag_pop : std_logic;
signal tag_mux_dat : t_tag; signal tag_mux_dat : t_tag;
signal tag_mux_empty : std_logic; signal tag_mux_empty : std_logic;
...@@ -84,19 +84,18 @@ architecture rtl of eb_slave_top is ...@@ -84,19 +84,18 @@ architecture rtl of eb_slave_top is
signal mux_wbm_pop : std_logic; signal mux_wbm_pop : std_logic;
signal wbm_mux_dat : t_wishbone_data; signal wbm_mux_dat : t_wishbone_data;
signal wbm_mux_empty : std_logic; signal wbm_mux_empty : std_logic;
begin begin
rstn_i <= nRst_i; rstn_i <= nRst_i;
EB_RX_o.ack <= EB_RX_i.cyc and EB_RX_i.stb and not rx_stall; EB_RX_o.ack <= EB_RX_i.cyc and EB_RX_i.stb and not rx_stall;
EB_RX_o.err <= '0'; EB_RX_o.err <= '0';
EB_RX_o.rty <= '0'; EB_RX_o.rty <= '0';
EB_RX_o.int <= '0';
EB_RX_o.stall <= rx_stall; EB_RX_o.stall <= rx_stall;
EB_RX_o.dat <= (others => '0'); EB_RX_o.dat <= (others => '0');
fsm : eb_slave_fsm fsm : eb_slave_fsm
port map( port map(
clk_i => clk_i, clk_i => clk_i,
rstn_i => rstn_i, rstn_i => rstn_i,
...@@ -122,7 +121,7 @@ begin ...@@ -122,7 +121,7 @@ begin
EB_TX_o.we <= '1'; EB_TX_o.we <= '1';
EB_TX_o.sel <= (others => '1'); EB_TX_o.sel <= (others => '1');
EB_TX_o.adr <= (others => '0'); EB_TX_o.adr <= (others => '0');
mux : eb_tx_mux mux : eb_tx_mux
port map ( port map (
clk_i => clk_i, clk_i => clk_i,
......
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