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# Schematics review report
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Date: 15.06.2018 - 20.07.2018
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Reviewers: T. Wlostowski, M. Rizzi, D. Lampridis, M. Ricci
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*Tom:**
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General:
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\- Title blocks to be updated, add OHWR licenses.
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Regulators:
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\- Add Pulldowns on power enable signals
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\- Change 3V7 to 3V8 and 1V4 to 1V6 to respect maximum dropout of the
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LDOs.
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PLL:
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\- Missing ground on cdcm61002 decoupling caps
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\- IC6 CS pin should not be grounded\!
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\- Add CS pin connections to the FPGA for both PLLs
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LED\_FP:
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\- don't use a PMOS to drive the LEDs (too high Vgson)
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Other:
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\- Add pulldowns for VCXO enable inputs
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\- Removed XADC (seems to not be used at all)
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\- Added net ties on PP12V and MTCA\_MP3V3
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\- Renamed MTCA.4 backplane connectors to follow the MTCA standard
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\- Changed pushbuttons to smaller ones
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\- Changed ARM debug pinhead to IDC with key
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\*Dimitris:
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\*
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- fpga\_board (node\_top)
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- fpga\_power
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\- extra wire at GND symbols and pin A1 on IC1M -\> junctions
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- transceivers
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\- add len match directive for calibration resistor (UG476,
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p303)
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- gtx\_data\_splitter
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\- IC25, pin 5 extra wire -\> junction
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- regulators
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\- LDOs have max dropout 400mV. Safer/more robust then to
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provide P1V5 and P3V8 instead of P1V4 and P3V7.
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\- T1, T3: INH/UVLO is connected through internal resistor
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divider to AGND. Should they (T1 and T3) also be connected to
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AGND ?
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- pll
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\- AD9516: safer/more robust to drive SPI CS only when you need
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it, instead of always 'on'
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- clk\_external
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\- AD9516: safer/more robust to drive SPI CS only when you need
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it, instead of always 'on'
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\- Diodes on TR3 secondary need refdes
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- sfp
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\- J3, J4, pins 9 and 31 extra wire -\> junction
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- rf board (rfboard\_top)
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- regulators
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\- Note says DC/DC set to 3.7, but net name says 3.6, Rset is
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3.65. Also, 0.35V less than LDO max dropout 0.4V. Safer/more
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robust to provide 3V8 instead.
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\- 5V is actually 4.98V, due to R155 being 56k instead of 56k2
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- RF generation
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\- drive SPI CS
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- RF distribution
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\- IC22, 23, 24, pin 4 extra wire -\> junction
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\- IC26, 27, 28, is EP grounded?
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\- IC26, 27, 28, why noERCs?
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- clk\_distribution
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\- drive 2x SPI CS
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*Maxime:**
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\- IC5: The CLK\_HELPER\_VCXO come in a capa that is pushed to P3V3A
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before go to XIN. Is that normal ? Or It's a mistake and only CE Have to
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be push to P3V3A ?
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\- AGND / GND of LMZ31704: Do you need a single net connect between AGND
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and GND or no connect between ?. I don't really understand your
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comment.
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Tom: there's no need for the net tie as AGND and GND are connected
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inside the chip.
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\- GTX Differential Pair. Could you review The “Transceivers” Page ? It
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is normal that for exemple “LINK0\_GTX\_TX\_FB\_P/N” goes not in BGA but
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“LINK0\_GTX\_TX\_P” goes on 2 different Pair of BGA ?
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Tom: this is a bug, the pins should be connected to FB pins. Fixed in
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the schematics.
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\- If we search “UNIV\_ID\_SDA” or SCL. We found that there is 2 with
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the same net name but not connected together. (Page “Management” and
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Page “FPGA\_local\_peripherals”). Should be connect all together. Or it
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is right ?
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Tom: these buses are separate, we could rename them to make this clear.
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