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# eRTM15 LLRF White Rabbit
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# High Performance White Rabbit Timing Receiver in MTCA.4 format.
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## Project description
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The eRTM15-LLRF-WR project is composed by two MTCA eRTM modules: a WR
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Node module and a RF module.
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The WR node is a eRTM module, designed to be inserted into eRTM Slot 14,
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with a redundant fiber connection to a White Rabbit network. It controls
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the RF module through a board-to-board connector.
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The RF module is designed to be inserted into eRTM Slot 15. It provides
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clocks and LO/REF signals through the specific LLRF backplane to µRTM
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and AMC
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slots.
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The HP WR Timing Receiver is composed by two MTCA eRTM (Rear Transition Module) modules:
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- Digital board (WR node), sitting in the slot 14. The board provides a redundant uplink to the WR network (2 SFP ports) and hosts the FPGA that implements the WR stack.
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- RF board, using the slot 15. This board produces the Local Oscillator/Reference RF signals using a DDS as well as two configurable digital LVPECL clocks. They are distributed to the RTM/AMC slots of a MTCA.4 crate through the [MTCA.4 RF Backplane](https://www.nateurope.com/products/formfactors/MicroTCA.4//NAT-LLRF-Backplane)
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The two boards always go together (stacked in a "sandwich" form) into the neighboring backplane slots 14 and 15. Inter-board communication is done through a high speed board-to-board cable.
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## Block Diagram
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[![](/uploads/d88429836fda644e836e7e5c3a353abd/wr-llrf-scheme.png)](/uploads/d88429836fda644e836e7e5c3a353abd/wr-llrf-scheme.png)
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-----
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## Main Features
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## Features
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- Kintex-7 FPGA on WR Main board
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- Redundant WR link connection
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- Deterministic gigabit transceiver (GTX) with hardware support
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for calibration
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- Control of the RF board through board-to-board connector
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- Front panel of WR Main board
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### Digital Board
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- Kintex-7 (XC7K70) FPGA
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- White Rabbit Core with redundant WR links
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- Fully deterministic gigabit transceiver (GTX) with no-phase-jump mode
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- Controls the RF board through the board-to-board connector
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- Front panel:
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- 2 SFP cages for White Rabbit input
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- PPS input and output connectors (SMA)
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- 10 MHz input (SMA)
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- WR clock output (SMA)
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- USB serial console
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- Front panel outputs of RF board
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- RTM clocks CLKA and CLKB
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- 2 LO Monitor
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- 2 REF Monitor
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- Zone-3 backplane connector of RF board
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- 11 RTM\_CLKA signals (62.5 MHz, 100 MHz, 125 MHz, 200 MHz, 250
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### RF Board
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- Front panel outputs:
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- RTM clocks CLKA and CLKB (SMA)
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- 2 LO Monitor (SMA)
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- 2 REF Monitor (SMA)
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- Zone-3 backplane connector:
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- 11 RTM\_CLKA signals (configurable: 62.5 MHz, 100 MHz, 125 MHz, 200 MHz, 250
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MHz, 500 MHz)
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- 11 RTM\_CLKB signals (62.5 MHz, 100 MHz, 125 MHz, 200 MHz, 250
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- 11 RTM\_CLKB signals (configurable: 62.5 MHz, 100 MHz, 125 MHz, 200 MHz, 250
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MHz, 500 MHz)
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- LVPECL clock signals with double termination, unused clocks can
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be shutdown
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be shut down.
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- Possibility to encode PPS and time-code information into CLKA
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and CLKB
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- Less than 100 fs RMS jitter (100 Hz - 5 MHz)
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- LO/REF/CAL backplane of RF board
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- LO/REF/CAL backplane connector (Radiall Coaxipack)
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- 9 LO signals, 10-250 MHz, 12 dBm
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- 9 REF signals, 10-250 MHz, 12 dBm
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- Less than 100 fs RMS jitter (100 Hz - 5 MHz)
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- RF power monitoring on all backplane RF signals
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- RF power monitoring on all backplane RF outputs
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- Unused RF channels can be internally terminated
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- Temperature sensors on LO and REF distribution sections
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- Unique IDs
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... | ... | @@ -55,8 +54,8 @@ slots. |
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links, one for storage)
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- One EUI-48 ID for RF board (storage)
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- STM32F microcontroller for MicroTCA management
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- Running FreeRTOS
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- Runs OpenMMC
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-----
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## Detailed project information
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... | ... | |