EMC2-DP
Project description
PC/104 OneBank Carrier for SoC Modules.
The EMC2-DP is a PCIe/104 OneBank Carrier for a Trenz compatible SoC Module and has expansion for a VITA57.1 FMC LPC I/O board and also has I/O pins, using a 100-way Samtec RazorBeam connectors system. The add-on board, called “Sundance External Interface Connector – SEIC” contains LEDs, RS232, USB2.0, HDMI, 1Gb Ethernet and SATA . The “SEIC” can be customize for individual applications and bespoke connectors.
The PCIe/104 OneBank design enables the EMC2-DP to be added to robust and rugged installations for various commercial, medial, industrial and military uses.
This development is made under the EU Artemis EMC2 project.
Main Features
- PCIe/104 OneBank Carrier for Trenz SoC Modules
- PCI Express Gen 2 compatible and integrate PCI Express switch
- Infinite number of EMC2-DP can be stacked for large I/O solutions
- Expandable with any VITA57.1 FMC I/O Module for more flexibility
- 96mm x 90 mm PC/104 Form-Factor with Cable-less Break-Out PCB Connector
Project information
- Demonstration example
Releases
Hardware
- Official production documentation: EDMS EDA-02839
- Pre-release design documentation: SPEXI-V1.0.zip
Demonstration example
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spexi_simpledemo.zip
The file spexi_simpledemo.zip contains a demo design and all the files including the .bit and .msc files which can be used to download this design to the SPEXI using Xilinx iMPACT and the download cable, or use the download path via the Gennum GN4124. This design contains the interface to the Gennum GN4124, an I2C master to access the FMC board eeprom, a carrier control and status register to get some information of the SPEXI carrier, and a GPIO register to access the four LEDs and the two buttons.
To download the .mcs file into the SPI memory (M25P128) you will need to configure iMPACT to access the SPI flash memory connector to the Spartan-6 150T.
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spexi_golden.zip
The file spexi_golden.zip contains the same design as spexi_simpledemo.zip but does not contain the GPIO register for the LEDs and buttons. This design is used to be able to get the first information from the SPEXI and the FMC to be able to determine which other FMC specific FPGA design could be loaded safely.
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spexi_pts.zip
The file spexi_pts.zip contains the complete set of VHDL/FPGA designs and corresponding phyton files for the Production Test Suite. This PTS is used to test the boards functionally after manufacturing. Because of this the designs also contain several examples of how to connect to the other interfaces on the SPEXI carrier.
Contacts
Commercial producers
General question about project
- Adriaan Rijllart - CERN - project initiator
- Erik van der Bij - CERN
Status
Date | Event |
11-05-2017 | Project added to https://www.ohwr.org. |
9 May 2017