... | ... | @@ -65,7 +65,22 @@ complex modules. |
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- do not end names of the signals in your modules with *i/\_o/\_b
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and do not begin signal names with s* (the optional naming
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convention from the guidelines that is not recommended)
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- whenever it is known/fixed, indicate the clock frequency in its
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name, i.e.: clk\_125m\_pllref, clk\_80m\_ADC, clk\_20m\_vcxo\_i
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- make sure that only needed signals are in sensitivity list of a
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process (e.g. if you use process with synchronous reset, make
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sure reset is not in sensitivity list)
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- do not use "new" and "old" in the names (the new will become old
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very fast and the name will mean nothing)
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- before starting to implement a module/function that is not specific
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to your project (say, it deals with Endianess or calculate CRC,
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check whether such a function is already in general-cores)
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- examples of non-clear code
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- before using asynchronous input signals (e.g. from DIO) in your
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synchronous design, first synchronise it with your clock domain and
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then deglitch the signal, preferably use
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gc\_async\_signals\_input\_stage in modules/common of
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[general-cores](https://www.ohwr.org/project/general-cores)
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- if your code is auto-generated (e.g. by wbgen2) do not modify it
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unless you are really sure what you do (usually, this never happens)
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- State copyright and license in all files, [see
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