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## VHDL Review Checklist
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Before any review, check whether your project/module follows the these
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simple tips (these are the usual remarks that you will get from
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reviewers)
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- Use registers in IOB for in/out to get well-defined timing,
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independent of routing
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- Check crossings of clock domains, use synchronizer stages when
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value). Behavior would be different if it was a variable
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- Provide minimum description in the header of each file, [see
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example](https://www.ohwr.org/4734)
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-----
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- Follow, as closely as possible, the suggested [file
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structure](https://www.ohwr.org/4472)
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\---
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## Wishbone bus
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