... | ... | @@ -100,7 +100,7 @@ receive from reviewers) |
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- If your code is auto-generated (e.g. by wbgen2) add a readme with
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how the commands for the auto-generation are invoked.
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- State copyright and license in all files, [see
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example](https://www.ohwr.org/4734)
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example](https://www.ohwr.org/project/ed/wikis/Documents/VHDL-coding-documents-and-files)
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- Follow good practices when using git, in specific for HDL designs:
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- git-ignore synthesis-generated and simulation-generated files
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- don't commit the "\*.xise" in syn/ folder unless it's in a
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... | ... | @@ -113,7 +113,7 @@ receive from reviewers) |
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- Set a signal, use value on line afterwards (takes 'previous'
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value). Behavior would be different if it was a variable
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- Provide minimum description in the header of each file, [see
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example](https://www.ohwr.org/4734)
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example](https://www.ohwr.org/project/ed/wikis/Documents/VHDL-coding-documents-and-files)
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- Follow, as closely as possible, the suggested [file
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structure](https://www.ohwr.org/4472)
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... | ... | |