... | ... | @@ -34,6 +34,24 @@ complex modules. |
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## VHDL Review Checklist - to be completed
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- Use registers in IOB for in/out to get well-defined timing,
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independent of routing
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- Check crossings of clock domains, use synchronizer stages when
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needed
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- Replace deep if-then statements by state machine
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- Resets synchronized: use as on data input of registers
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- State machine recover from illegal states
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<!-- end list -->
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- examples of non-clear code
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- Set a signal, use value on line afterwards (takes 'previous'
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value). Behavior would be different if it was a variable
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-----
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## Wishbone bus
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Many Open designs use the Wishbone specification. You may want to
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... | ... | @@ -100,5 +118,5 @@ at CERN, I think they are still valid and useful. |
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-----
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Erik van der Bij - 2 February 2016
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Erik van der Bij - 23 May 2016
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