Define the CPCI-S signal assignment of the 5 SHARED_BUS lines
It should be defined which lines provide the five SHARED_BUS nets by referring to their CPCI-S names, much like it is defined in sections 2.1.6-7 which lines can (optionally) carry the MGT and clock signals. The assignments used in the Zynq-Ultrascale-based system board (and adopted by the Igloo2-based one) are shown on the table below:
CPCI-S | SHARED_BUS bit |
---|---|
SATA_SL | 4 |
SATA_SCL | 3 |
SATA_SDO | 2 |
SATA_SDI | 1 |
WAKE_IN_N | 0 |