add synchronizers for nanoFIP rdy signals

8d1a2d7e · Grzegorz Daniluk · c7f28532 · 8d1a2d7e
Commit 8d1a2d7e authored Nov 27, 2018 by Grzegorz Daniluk
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Showing with 37 additions and 6 deletions

gefe_top.vhd hdl/top/gefe_test/gefe_top.vhd +37 -6

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--- a/hdl/top/gefe_test/gefe_top.vhd
+++ b/hdl/top/gefe_test/gefe_top.vhd
@@ -129,9 +129,12 @@ architecture rtl of gefe_top is
  signal scl_out, sda_out  : std_logic;
  signal scl_oen, sda_oen  : std_logic;

-  signal slots_in  : t_wic_slot_in_array(c_SLOT_NUM-1 downto 0);
-  signal slots_out : t_wic_slot_out_array(c_SLOT_NUM-1 downto 0);
-  signal diags     : t_diag_out;
+  signal slots_in        : t_wic_slot_in_array(c_SLOT_NUM-1 downto 0);
+  signal slots_out       : t_wic_slot_out_array(c_SLOT_NUM-1 downto 0);
+  signal diags           : t_diag_out;
+  signal var1_rdy_synced : std_logic;
+  signal var2_rdy_synced : std_logic;
+  signal var3_rdy_synced : std_logic;

 begin

@@ -174,6 +177,34 @@ begin
  rst_n <= '1' when and_reduce(std_logic_vector(rst_cnt))='1' else
           '0';

+-------------------------------------------------------------------------------
+-- Synchronizers for RDY signals (40MHz clock domain in nanoFIP
+-------------------------------------------------------------------------------
+  cmp_sync_ffs_var1: entity work.gc_sync_ffs
+    port map(
+      clk_i    => clk_25m_i,
+      rst_n_i  => rst_n,
+      data_i   => var1_rdy_i,
+      synced_o => var1_rdy_synced,
+      npulse_o => open,
+      ppulse_o => open);
+  cmp_sync_ffs_var2: entity work.gc_sync_ffs
+    port map(
+      clk_i    => clk_25m_i,
+      rst_n_i  => rst_n,
+      data_i   => var2_rdy_i,
+      synced_o => var2_rdy_synced,
+      npulse_o => open,
+      ppulse_o => open);
+  cmp_sync_ffs_var3: entity work.gc_sync_ffs
+    port map(
+      clk_i    => clk_25m_i,
+      rst_n_i  => rst_n,
+      data_i   => var3_rdy_i,
+      synced_o => var3_rdy_synced,
+      npulse_o => open,
+      ppulse_o => open);
+
 -------------------------------------------------------------------------------

  cmp_wic_main: entity work.wic_main
@@ -199,11 +230,11 @@ begin
    rstin_o    => rstin_o,
    nostat_o   => nostat_o,
    var3_acc_o => var3_acc_o,
-    var3_rdy_i => var3_rdy_i,
+    var3_rdy_i => var3_rdy_synced,
    var2_acc_o => var2_acc_o,
-    var2_rdy_i => var2_rdy_i,
+    var2_rdy_i => var2_rdy_synced,
    var1_acc_o => var1_acc_o,
-    var1_rdy_i => var1_rdy_i,
+    var1_rdy_i => var1_rdy_synced,
    p3_lgth_o  => p3_lgth_o);

 -------------------------------------------------------------------------------