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DIOT WIC Gateware
DIOT WIC Gateware
Commit 7790d589 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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gefe_top: adding button input for reset

parent 34b96c26
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Showing with 5 additions and 2 deletions
hdl/top/gefe_test/gefe_top.pdc
View file @ 7790d589
......@@ -7,6 +7,7 @@ set_iobank Bank7 -vcci 2.50 -fixed ye
## I/Os assignments
set_io {clk_25m_i} -pinname R1 -fixed YES -iostd LVCMOS25 -register NO -res_pull NONE -schmitt_trigger OFF -in_delay OFF
set_io {button_i} -pinname B3 -fixed YES -iostd LVCMOS25 -register NO -res_pull NONE -schmitt_trigger OFF -in_delay OFF
set_io {ack_i} -pinname K4 -fixed YES -iostd LVCMOS25 -register NO -res_pull NONE -schmitt_trigger OFF -in_delay OFF
set_io {adr_o[0]} -pinname F3 -fixed YES -iostd LVCMOS25 -register NO -res_pull NONE
set_io {adr_o[1]} -pinname G3 -fixed YES -iostd LVCMOS25 -register NO -res_pull NONE
......
hdl/top/gefe_test/gefe_top.vhd
View file @ 7790d589
......@@ -40,6 +40,7 @@ use unisim.vcomponents.all;
entity gefe_top is
port (
clk_25m_i : in std_logic;
button_i : in std_logic;
-- nanoFIP Wishbone
dat_i : in std_logic_vector(7 downto 0);
......@@ -128,7 +129,8 @@ begin
end if;
end if;
end process;
rst_n <= '1' when and_reduce(std_logic_vector(rst_cnt))='1' else '0';
rst_n <= '1' when (and_reduce(std_logic_vector(rst_cnt))='1' and button_i = '0') else
'0';
-------------------------------------------------------------------------------
......@@ -186,7 +188,7 @@ GEN_IO_EMULATOR: if c_IO_EMULATION = true generate
cmp_wic_simulator: entity work.wic_simulator
generic map (
g_SIMULATION => false,
g_ENABLE => true)
g_ENABLE => false)
port map (
rst_n_i => rst_n,
clk_i => clk_25m_i,
......
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