Commit 252483b4 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk

wic_main: simplify periodic VAR3 updating

There is no need for updating it periodically with a counter. It's enough to
update it after previous VAR3 was produced (even if there was no change in
inputs).
parent c7dfc62b
......@@ -91,7 +91,6 @@ architecture rtl of wic_main is
constant c_NF_VAR_MAXSIZE : unsigned(9 downto 0) := to_unsigned(124, 10);
--------------------------
constant c_UPDATE_PERIOD : unsigned(15 downto 0) := x"FFFF";
type t_state is (IDLE, READ_LEN, READ_VAR1, WRITE_VAR3);
signal state : t_state;
......@@ -106,7 +105,7 @@ architecture rtl of wic_main is
signal var1_read : std_logic;
-- VAR3 producing
signal refresh_cnt : unsigned(15 downto 0);
signal var3_rdy_d0 : std_logic;
signal var3_reg : t_wic_var;
signal var3_refresh : std_logic; -- triggers sending status of all inputs
signal var3_written : std_logic;
......@@ -316,23 +315,22 @@ begin
loops_changed <= '1' when(f_detect_change(slots_in_synced, slots_in_reg, g_NUM)) else
'0';
-- Counter for periodic VAR3 updates
-- process monitors when a refresh of VAR3 should be triggered
process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
var3_refresh <= '0';
refresh_cnt <= (others=>'0');
in_error <= '0'; -- TODO: add loops toggling detection
var3_rdy_d0 <= '0';
else
if refresh_cnt = c_UPDATE_PERIOD or loops_changed = '1' then
var3_rdy_d0 <= var3_rdy_i;
if (var3_rdy_d0 = '0' and var3_rdy_i = '1') or loops_changed = '1' then
-- force the state machine to write VAR3 if inputs have changed, or
-- at least after previous VAR3 was read - to show that we're alive.
var3_refresh <= '1';
refresh_cnt <= (others=>'0');
elsif var3_written = '1' then
var3_refresh <= '0';
refresh_cnt <= refresh_cnt + 1;
else
refresh_cnt <= refresh_cnt + 1;
end if;
end if;
end if;
......
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