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DIOT WIC Gateware
DIOT WIC Gateware
Commit 1e965514 authored by Tristan Gingold's avatar Tristan Gingold
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diot_urv_top: first working demo (leds).

parent 467b5c82
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hdl/rtl/urv_wic/fip_urv.vhd
View file @ 1e965514
...@@ -28,12 +28,14 @@ use ieee.std_logic_1164.all; ...@@ -28,12 +28,14 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;
use work.genram_pkg.all; use work.genram_pkg.all;
use work.memory_loader_pkg.all;
use work.wishbone_pkg.all; use work.wishbone_pkg.all;
use work.urv_pkg.all; use work.urv_pkg.all;
entity fip_urv is entity fip_urv is
generic( generic(
g_IRAM_LOG_SIZE : natural := 14; g_IRAM_LOG_SIZE : natural := 12;
g_DRAM_LOG_SIZE : natural := 12;
g_IRAM_INIT : string); g_IRAM_INIT : string);
port( port(
clk_sys_i : in std_logic; clk_sys_i : in std_logic;
...@@ -89,7 +91,6 @@ architecture arch of fip_urv is ...@@ -89,7 +91,6 @@ architecture arch of fip_urv is
signal dm_data_write : std_logic; signal dm_data_write : std_logic;
signal dwb_out : t_wishbone_master_out; signal dwb_out : t_wishbone_master_out;
signal bus_timeout_cnt : unsigned(7 downto 0);
begin begin
dwb_o <= dwb_out; dwb_o <= dwb_out;
...@@ -126,36 +127,41 @@ begin ...@@ -126,36 +127,41 @@ begin
dm_data_write <= not dm_is_wishbone and dm_store; dm_data_write <= not dm_is_wishbone and dm_store;
U_iram : generic_dpram p_rom: process (clk_sys_i)
generic map ( is
g_DATA_WIDTH => 32, constant IRAM_WSIZE : natural := 2 ** (g_IRAM_LOG_SIZE - 2);
g_SIZE => 2**(g_IRAM_LOG_SIZE - 2), constant mem : t_ram32_type(0 to IRAM_WSIZE - 1) :=
g_WITH_BYTE_ENABLE => TRUE, f_load_mem32_from_file (g_IRAM_INIT, IRAM_WSIZE, True);
g_ADDR_CONFLICT_RESOLUTION => "dont_care", begin
g_INIT_FILE => g_IRAM_INIT, if rising_edge(clk_sys_i) then
g_FAIL_IF_FILE_NOT_FOUND => FALSE, im_data <= mem (to_integer(unsigned(im_addr(g_IRAM_LOG_SIZE - 1 downto 2))));
g_DUAL_CLOCK => FALSE) end if;
port map ( end process;
rst_n_i => rst_n_i,
clka_i => clk_sys_i,
bwea_i => "1111",
wea_i => '0',
aa_i => im_addr(g_IRAM_LOG_SIZE - 1 downto 2),
da_i => x"0000_0000",
qa_o => im_data,
clkb_i => clk_sys_i,
bweb_i => dm_data_select,
web_i => dm_data_write,
ab_i => dm_addr(g_IRAM_LOG_SIZE - 1 downto 2),
db_i => dm_data_s,
qb_o => dm_mem_rdata);
-- 1st MByte of the mem is the IRAM -- 1st MByte of the mem is the IRAM
dm_is_wishbone <= '1' when dm_addr(31 downto 20) /= x"000" else '0'; dm_is_wishbone <= '1' when dm_addr(31 downto 20) /= x"000" else '0';
dm_data_write <= not dm_is_wishbone and dm_store; dm_data_write <= not dm_is_wishbone and dm_store;
dm_data_l <= dm_wb_rdata when dm_select_wb = '1' else dm_mem_rdata; dm_data_l <= dm_wb_rdata when dm_select_wb = '1' else dm_mem_rdata;
p_ram: process (clk_sys_i)
is
variable mem : t_ram32_type (2**(g_DRAM_LOG_SIZE - 2) - 1 downto 0);
variable addr : natural range mem'range;
begin
if rising_edge(clk_sys_i) then
addr := to_integer(unsigned(dm_addr(g_DRAM_LOG_SIZE - 1 downto 2)));
dm_mem_rdata <= mem(addr);
if dm_data_write = '1' then
for i in 0 to 3 loop
if dm_data_select (i) = '1' then
mem(addr)(8*i + 7 downto 8*i) := dm_data_s(8*i + 7 downto 8*i);
end if;
end loop;
end if;
end if;
end process;
-- Wishbone bus arbitration / internal RAM access -- Wishbone bus arbitration / internal RAM access
p_wishbone_master : process(clk_sys_i) p_wishbone_master : process(clk_sys_i)
begin begin
...@@ -202,7 +208,6 @@ begin ...@@ -202,7 +208,6 @@ begin
dm_load_done <= '0'; dm_load_done <= '0';
dm_store_done <= '0'; dm_store_done <= '0';
dm_cycle_in_progress <= '1'; dm_cycle_in_progress <= '1';
bus_timeout_cnt <= (others => '0');
else else
dm_store_done <= '0'; dm_store_done <= '0';
dm_load_done <= '0'; dm_load_done <= '0';
...@@ -215,9 +220,7 @@ begin ...@@ -215,9 +220,7 @@ begin
dwb_out.stb <= '0'; dwb_out.stb <= '0';
end if; end if;
bus_timeout_cnt <= bus_timeout_cnt + 1; if dwb_i.ack = '1' then
if dwb_i.ack = '1' or bus_timeout_cnt = 100 then
if dm_wb_write = '0' then if dm_wb_write = '0' then
dm_wb_rdata <= f_x_to_zero(dwb_i.dat); dm_wb_rdata <= f_x_to_zero(dwb_i.dat);
dm_select_wb <= '1'; dm_select_wb <= '1';
......
hdl/syn/diot_urv_demo/Manifest.py
View file @ 1e965514
...@@ -11,4 +11,6 @@ syn_project = "diot_urv_demo" ...@@ -11,4 +11,6 @@ syn_project = "diot_urv_demo"
top_module = "diot_urv_top" top_module = "diot_urv_top"
syn_tool = "libero" syn_tool = "libero"
files = ['diot_wic_demo.pdc', 'diot_wic_demo.sdc']
modules = { "local" : [ "../../top/diot_urv_demo"] } modules = { "local" : [ "../../top/diot_urv_demo"] }
hdl/syn/diot_urv_demo/diot_wic_demo.pdc 0 → 100644
View file @ 1e965514
This diff is collapsed.
hdl/syn/diot_urv_demo/diot_wic_demo.sdc 0 → 100644
View file @ 1e965514
# Top Level Design Parameters
# Clocks
create_clock -name {diot_wic_top|clk_25m_i} -period 40.000000 -waveform {0.000000 20.000000} clk_25m_i
# False Paths Between Clocks
# False Path Constraints
# Maximum Delay Constraints
# Multicycle Constraints
# Virtual Clocks
# Output Load Constraints
# Driving Cell Constraints
# Wire Loads
# set_wire_load_mode top
# Other Constraints
hdl/top/diot_urv_demo/diot_urv_top.vhd
View file @ 1e965514
...@@ -73,8 +73,8 @@ entity diot_urv_top is ...@@ -73,8 +73,8 @@ entity diot_urv_top is
s1_p_b : inout std_logic_vector(15 downto 0); s1_p_b : inout std_logic_vector(15 downto 0);
s1_n_b : inout std_logic_vector(15 downto 0); s1_n_b : inout std_logic_vector(15 downto 0);
s1_en_i : in std_logic; s1_en_i : in std_logic;
s2_p_b : inout std_logic_vector(21 downto 0); s2_p_b : inout std_logic_vector(13 downto 0);
s2_n_b : inout std_logic_vector(21 downto 0); s2_n_b : inout std_logic_vector(13 downto 0);
s2_en_i : in std_logic; s2_en_i : in std_logic;
s3_p_b : inout std_logic_vector(13 downto 0); s3_p_b : inout std_logic_vector(13 downto 0);
s3_n_b : inout std_logic_vector(13 downto 0); s3_n_b : inout std_logic_vector(13 downto 0);
...@@ -162,7 +162,7 @@ begin ...@@ -162,7 +162,7 @@ begin
begin begin
if rising_edge(clk_25m_i) then if rising_edge(clk_25m_i) then
if (por_n_d(1) = '0' or button_i = '1') then if (por_n_d(1) = '0' or button_i = '1') then
rst_cnt <= (others=>'1'); rst_cnt <= x"0004"; -- (others=>'1');
elsif rst_cnt /= (15 downto 0 => '0') then elsif rst_cnt /= (15 downto 0 => '0') then
rst_cnt <= rst_cnt - 1; rst_cnt <= rst_cnt - 1;
end if; end if;
...@@ -191,7 +191,7 @@ begin ...@@ -191,7 +191,7 @@ begin
inst_fip_urv: entity work.fip_urv inst_fip_urv: entity work.fip_urv
generic map ( generic map (
g_iram_init => "" g_iram_init => "../../../sw/fip_urv/fip_urv.ram"
) )
port map ( port map (
clk_sys_i => clk_25m_i, clk_sys_i => clk_25m_i,
...@@ -280,7 +280,7 @@ begin ...@@ -280,7 +280,7 @@ begin
slots_in(4).loops(13 downto 0) <= s5_p_b(13 downto 0); slots_in(4).loops(13 downto 0) <= s5_p_b(13 downto 0);
slots_in(5).loops <= s7_p_b(15 downto 0); slots_in(5).loops <= s7_p_b(15 downto 0);
s1_n_b(15 downto 0) <= slots_out(0).relays; s1_n_b(15 downto 0) <= slots_out(0).relays;
s2_n_b(15 downto 0) <= slots_out(1).relays; s2_n_b(13 downto 0) <= slots_out(1).relays(13 downto 0);
s3_n_b(13 downto 0) <= slots_out(2).relays(13 downto 0); s3_n_b(13 downto 0) <= slots_out(2).relays(13 downto 0);
s4_n_b(13 downto 6) <= slots_out(3).relays(8 downto 1); s4_n_b(13 downto 6) <= slots_out(3).relays(8 downto 1);
s4_n_b(3) <= slots_out(3).relays(0); s4_n_b(3) <= slots_out(3).relays(0);
...@@ -294,7 +294,10 @@ begin ...@@ -294,7 +294,10 @@ begin
slots_in(4).loops(15 downto 14) <= (others=>'0'); slots_in(4).loops(15 downto 14) <= (others=>'0');
end block; end block;
GEN_LEDS_O: for I in 0 to 5 generate -- Leds: assign to '0' to switch on the led, 'Z' to switch off.
leds_o(0) <= '0' when rst_n = '0' or leds(0) = '1' else '1';
GEN_LEDS_O: for I in 1 to 5 generate
leds_o(I) <= '0' when leds(I) = '1' else leds_o(I) <= '0' when leds(I) = '1' else
'Z'; 'Z';
end generate; end generate;
......
sw/fip_urv/Makefile
View file @ 1e965514
...@@ -13,7 +13,7 @@ CFLAGS = -mabi=ilp32 -march=rv32im -O ...@@ -13,7 +13,7 @@ CFLAGS = -mabi=ilp32 -march=rv32im -O
OBJS = crt0.o $(OUTPUT).o OBJS = crt0.o $(OUTPUT).o
LDS = ram.ld LDS = ram.ld
all: $(OUTPUT).hex all: $(OUTPUT).ram
fip_urv_regs.h: ../../hdl/rtl/urv_wic/fip_urv_regs.cheby fip_urv_regs.h: ../../hdl/rtl/urv_wic/fip_urv_regs.cheby
cheby --gen-c=$@ -i $< cheby --gen-c=$@ -i $<
...@@ -21,7 +21,7 @@ fip_urv_regs.h: ../../hdl/rtl/urv_wic/fip_urv_regs.cheby ...@@ -21,7 +21,7 @@ fip_urv_regs.h: ../../hdl/rtl/urv_wic/fip_urv_regs.cheby
%.bin: %.elf %.bin: %.elf
${OBJCOPY} -O binary $< $@ ${OBJCOPY} -O binary $< $@
%.hex: %.bin %.ram: %.bin
./tobin.py $< > $@ ./tobin.py $< > $@
$(OUTPUT).elf: $(LDS) $(OBJS) $(OUTPUT).elf: $(LDS) $(OBJS)
...@@ -29,7 +29,7 @@ $(OUTPUT).elf: $(LDS) $(OBJS) ...@@ -29,7 +29,7 @@ $(OUTPUT).elf: $(LDS) $(OBJS)
$(SIZE) $@ $(SIZE) $@
clean: clean:
rm -f $(OUTPUT).elf $(OUTPUT).bin $(OUTPUT).hex $(OBJS) rm -f $(OUTPUT).elf $(OUTPUT).bin $(OUTPUT).ram $(OBJS)
%.o: %.S %.o: %.S
${XCC} -c $(CFLAGS) $< -o $@ ${XCC} -c $(CFLAGS) $< -o $@
......
sw/fip_urv/fip_urv.c
View file @ 1e965514
...@@ -17,7 +17,7 @@ main (void) ...@@ -17,7 +17,7 @@ main (void)
{ {
/* Check for FIP message. */ /* Check for FIP message. */
regs->leds = leds; regs->leds = leds;
leds = ((leds << 1) & 0x3f) | ((leds >> 6) & 1); leds = ((leds << 1) & 0x3f) | ((leds >> 5) & 1);
for (j = 0; j < 1000000; j++) for (j = 0; j < 1000000; j++)
asm volatile ("nop"); asm volatile ("nop");
} }
......
sw/fip_urv/tobin.py
View file @ 1e965514
...@@ -12,7 +12,7 @@ def main(): ...@@ -12,7 +12,7 @@ def main():
sys.exit("length of {} is not a multiple of 4".format(filename)) sys.exit("length of {} is not a multiple of 4".format(filename))
for i in range(0, len(b), 4): for i in range(0, len(b), 4):
v, = struct.unpack('<I', b[i:i+4]) v, = struct.unpack('<I', b[i:i+4])
print('{:08x}'.format(v)) print('{:032b}'.format(v))
if __name__ == '__main__': if __name__ == '__main__':
main() main()
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