Merge branch 'basic_monitoring'

0f4bd87e · Grzegorz Daniluk · d9794793 · b801a36c · 0f4bd87e · 0f4bd87e
Commit 0f4bd87e authored Aug 16, 2018 by Grzegorz Daniluk
22 changed files
--- a/hdl/rtl/Manifest.py
+++ b/hdl/rtl/Manifest.py
 modules = {
-        "local" : ["wic_modules"]}
+        "local" : ["wic_modules", "diot_diag"]}
--- a/hdl/rtl/diot_diag/Manifest.py
+++ b/hdl/rtl/diot_diag/Manifest.py
+files = ["diag_pkg.vhd", "diot_diag.vhd"];
--- a/hdl/rtl/diot_diag/diag_pkg.vhd
+++ b/hdl/rtl/diot_diag/diag_pkg.vhd
+-------------------------------------------------------------------------------
+-- Title      : DIOT Demo Diagnostics package
+-- Project    : Distributed I/O Tier
+-------------------------------------------------------------------------------
+-- File       : diag_pkg.vhd
+-- Author     : Greg Daniluk <grzegorz.daniluk@cern.ch>
+-- Company    : CERN (BE-CO-HT)
+-- Standard   : VHDL
+-------------------------------------------------------------------------------
+-- Description:
+-- This package defines types and constants used by diot_diag module.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2018 CERN
+--
+-- Copyright and related rights are licensed under the Solderpad Hardware
+-- License, Version 0.51 (the “License”) (which enables you, at your option,
+-- to treat this file as licensed under the Apache License 2.0); you may not
+-- use this file except in compliance with the License. You may obtain a copy
+-- of the License at http://solderpad.org/licenses/SHL-0.51.
+-- Unless required by applicable law or agreed to in writing, software,
+-- hardware and materials distributed under this License is distributed on an
+-- “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- or implied. See the License for the specific language governing permissions
+-- and limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+package diag_pkg is
+
+  constant c_CMD_FAN_STAT  : integer := 0;
+  constant c_CMD_TEMP_STAT : integer := 1;
+  constant c_CMD_VOLT_STAT : integer := 2;
+  constant c_CMD_FAN_SPEED : integer := 3;
+  constant c_CMD_TEMP      : integer := 4;
+  
+  type t_diag_buf is array (natural range<>) of std_logic_vector(7 downto 0);
+
+  type t_diag_out is record
+    fan_status  : std_logic_vector(7 downto 0);
+    temp_status : std_logic_vector(7 downto 0);
+    volt_status : std_logic_vector(7 downto 0);
+    fans_speed  : t_diag_buf(0 to 5); -- 3 fans, each speed 2 bytes
+    temps       : t_diag_buf(0 to 5);
+  end record;
+
+  constant c_DIAGS_DUMMY : t_diag_out := (x"CA", x"FE", x"BE",
+    (x"01", x"02", x"03", x"04", x"05", x"06"),
+    (x"11", x"12", x"13", x"14", x"15", x"16"));
+
+end diag_pkg;
--- a/hdl/rtl/diot_diag/diot_diag.vhd
+++ b/hdl/rtl/diot_diag/diot_diag.vhd
--- a/hdl/rtl/wic_modules/wic_main.vhd
+++ b/hdl/rtl/wic_modules/wic_main.vhd
@@ -32,6 +32,7 @@ library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 use work.wic_pkg.all;
+use work.diag_pkg.all;

 entity wic_main is
  generic (
@@ -43,6 +44,9 @@ entity wic_main is
    slots_i   : in  t_wic_slot_in_array(g_NUM-1 downto 0);
    slots_o   : out t_wic_slot_out_array(g_NUM-1 downto 0);

+    -- diagnostics data
+    diags_i   : in  t_diag_out;
+
    -- nanoFIP Wishbone
    wb_cyc_o  : out std_logic;
    wb_stb_o  : out std_logic;
@@ -306,7 +310,7 @@ begin
  -- TODO: add synchronizers for bckpl_loops_n_i

  -- VAR3: pack loops inputs to VAR3 bytes
-  var3_reg <= f_pack_var3(slots_in_synced, g_NUM);
+  var3_reg <= f_pack_var3(slots_in_synced, g_NUM, diags_i);

  -- detect if state of any loop has changed, it's a trigger to produce new VAR3
  loops_changed <= '1' when(f_detect_change(slots_in_synced, slots_in_reg, g_NUM)) else

--- a/hdl/rtl/wic_modules/wic_pkg.vhd
+++ b/hdl/rtl/wic_modules/wic_pkg.vhd
@@ -29,12 +29,19 @@

 library ieee;
 use ieee.std_logic_1164.all;
+use work.diag_pkg.all;

 package wic_pkg is
  
  constant c_IOS_SLOT   : integer := 16;
  constant c_BYTES_SLOT : integer := 4;

+  constant c_VAR3_FAN_ST_OFFSET  : integer := 64;
+  constant c_VAR3_TEMP_ST_OFFSET : integer := 65;
+  constant c_VAR3_VOLT_ST_OFFSET : integer := 66;
+  constant c_VAR3_FANS_OFFSET    : integer := 67;
+  constant c_VAR3_TEMP_OFFSET    : integer := 73;
+
  type t_wic_slot_in is record
    loops : std_logic_vector(c_IOS_SLOT-1 downto 0);
  end record;
@@ -53,7 +60,7 @@ package wic_pkg is
  type t_wic_var is array (0 to 123) of std_logic_vector(7 downto 0);

  function f_parse_var1 (var : t_wic_var; slot : integer) return t_wic_slot_out;
-  function f_pack_var3 (slot_array : t_wic_slot_in_array; slots : integer) return t_wic_var;
+  function f_pack_var3 (slot_array : t_wic_slot_in_array; slots : integer; diags : t_diag_out) return t_wic_var;
  function f_detect_change (current : t_wic_slot_in_array; prev : t_wic_slot_in_array; slots : integer) return boolean;

 end wic_pkg;
@@ -85,7 +92,7 @@ package body wic_pkg is
  -- Packs state of input loops into a nanoFIP VAR3 bytes. Takes into account
  -- VAR3 layout - how many bytes per slot should be used.
  -----------------------------------------------------------------------------
-  function f_pack_var3 (slot_array : t_wic_slot_in_array; slots : integer)
+  function f_pack_var3 (slot_array : t_wic_slot_in_array; slots : integer; diags : t_diag_out)
    return t_wic_var is
    variable i, ui : integer;
    variable sl : integer;
@@ -107,6 +114,16 @@ package body wic_pkg is
        i := i + 1;
      end loop;
    end loop;
+    -- fill monitoring data
+    tmp_var(c_VAR3_FAN_ST_OFFSET)  := diags.fan_status;
+    tmp_var(c_VAR3_TEMP_ST_OFFSET) := diags.temp_status;
+    tmp_var(c_VAR3_VOLT_ST_OFFSET) := diags.volt_status;
+    for i in 0 to diags.fans_speed'high loop
+      tmp_var(c_VAR3_FANS_OFFSET+i) := diags.fans_speed(i);
+    end loop;
+    for i in 0 to diags.temps'high loop
+      tmp_var(c_VAR3_TEMP_OFFSET+i) := diags.temps(i);
+    end loop;
    return tmp_var;
  end function;


--- a/hdl/sim/Manifest.py
+++ b/hdl/sim/Manifest.py
 files = [ "fip_device.svh", "fip_frame.svh", "fip_hardware_model.svh",
-        "fip_phy_model.svh", "fip_virtual_master.svh" ]
+        "fip_phy_model.svh", "fip_virtual_master.svh", "fcm2_interface.svh" ]
+
+include_dirs = [ "include", "include/wb" ]
+modules = {"local" : ["fcm2"]}
--- a/hdl/sim/fcm2/Manifest.py
+++ b/hdl/sim/fcm2/Manifest.py
+files = [ "pentair_fcm2_model.sv" ]
+
--- a/hdl/sim/fcm2/pentair_fcm2_model.sv
+++ b/hdl/sim/fcm2/pentair_fcm2_model.sv
+//-----------------------------------------------------------------------------
+// Title      : Pentair FCM2 simulation model
+// Project    : Distributed I/O Tier
+//-----------------------------------------------------------------------------
+// File       : pentair_fcm2_model.sv
+// Author     : Greg Daniluk <grzegorz.daniluk@cern.ch>
+// Company    : CERN (BE-CO-HT)
+// Standard   : VHDL
+//-----------------------------------------------------------------------------
+// Description:
+// This module is a simulation model for Pentair FCM2 diagnostics module. It
+// uses I2C slave implementation from general-cores repository and FCM_interface
+// to generate randomized monitoring data.
+//-----------------------------------------------------------------------------
+//
+// Copyright (c) 2018 CERN
+//
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 0.51 (the “License”) (which enables you, at your option,
+// to treat this file as licensed under the Apache License 2.0); you may not
+// use this file except in compliance with the License. You may obtain a copy
+// of the License at http://solderpad.org/licenses/SHL-0.51.
+// Unless required by applicable law or agreed to in writing, software,
+// hardware and materials distributed under this License is distributed on an
+// “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+// or implied. See the License for the specific language governing permissions
+// and limitations under the License.
+//
+//-----------------------------------------------------------------------------
+
+`include "../fcm2_interface.svh"
+
+module pentair_fcm2_model (clk_i, rst_n_i, sda_b, scl_b);
+  input clk_i;
+  input rst_n_i;
+  inout sda_b;
+  inout scl_b;
+
+  reg [7:0] fan_status;
+  reg [7:0] temp_status;
+  reg [7:0] volt_status;
+  reg [0:11] [7:0] fan_speed;
+
+  wire scl_out, scl_en;
+  wire sda_out, sda_en;
+
+  FCM_interface ctrl(clk_i, rst_n_i);
+
+  always @(posedge clk_i) begin
+    fan_status  = 'hCA;
+    temp_status = 'hFE;
+    volt_status = 'h01;
+    fan_speed   = 'hDEADBEEFBABE010203040506;
+  end
+
+  gc_i2c_slave #(
+    .g_auto_addr_ack(1))
+  i2c_slave (
+    .clk_i(clk_i),
+    .rst_n_i(rst_n_i),
+    .scl_i(scl_b),
+    .scl_o(scl_out),
+    .scl_en_o(scl_en),
+    .sda_i(sda_b),
+    .sda_o(sda_out),
+    .sda_en_o(sda_en),
+    .i2c_addr_i   (ctrl.dev_adr),
+    .ack_i        (ctrl.ack),
+    .tx_byte_i    (ctrl.tx_byte),
+    .rx_byte_o    (ctrl.rx_byte),
+    .i2c_sta_p_o  (ctrl.sta_p),
+    .i2c_sto_p_o  (ctrl.sto_p),
+    .addr_good_p_o(ctrl.adr_good_p),
+    .r_done_p_o   (ctrl.r_done),
+    .w_done_p_o   (ctrl.w_done)
+  );
+
+  assign scl_b = (scl_en)? scl_out : 'bz;
+  assign sda_b = (sda_en)? sda_out : 'bz;
+
+  always begin
+    ctrl.new_values();
+    ctrl.reply();
+  end
+
+endmodule
--- a/hdl/sim/fcm2_interface.svh
+++ b/hdl/sim/fcm2_interface.svh
+//-----------------------------------------------------------------------------
+// Title      : Pentair FCM2 simulation interface
+// Project    : Distributed I/O Tier
+//-----------------------------------------------------------------------------
+// File       : fcm2_interface.svh
+// Author     : Greg Daniluk <grzegorz.daniluk@cern.ch>
+// Company    : CERN (BE-CO-HT)
+// Standard   : VHDL
+//-----------------------------------------------------------------------------
+// Description:
+// This interface for FCM2 simulation model mimics Pentair FCM2 diagnostics
+// module using i2c_slave from general-cores repository.
+//-----------------------------------------------------------------------------
+//
+// Copyright (c) 2018 CERN
+//
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 0.51 (the “License”) (which enables you, at your option,
+// to treat this file as licensed under the Apache License 2.0); you may not
+// use this file except in compliance with the License. You may obtain a copy
+// of the License at http://solderpad.org/licenses/SHL-0.51.
+// Unless required by applicable law or agreed to in writing, software,
+// hardware and materials distributed under this License is distributed on an
+// “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+// or implied. See the License for the specific language governing permissions
+// and limitations under the License.
+//
+//-----------------------------------------------------------------------------
+//
+// FCM2 commands layout:
+// read i2c address: 0x39
+// cmd 0: fan  status (return 1 Byte)
+// cmd 1: temp status (return 1 Byte)
+// cmd 2: volt status (return 1 Byte)
+// cmd 3: fans speed  (return 12 Bytes) - 2B per fan
+// cmd 4: temperature (return 6 Bytes)  - 1B per sensor
+//
+//-----------------------------------------------------------------------------
+
+interface FCM_interface (input clk_i, rst_n_i);
+
+  logic [6:0] dev_adr;
+  logic ack;
+  logic [7:0] tx_byte;
+  logic [7:0] rx_byte;
+  wire sta_p;
+  wire sto_p;
+  wire adr_good_p;
+  wire r_done;
+  wire w_done;
+
+  reg [7:0] fan_status;
+  reg [7:0] temp_status;
+  reg [7:0] volt_status;
+  reg [0:11] [7:0] fan_speed;
+  reg [0:5] [7:0] temps;
+
+  // set default values on reset
+  initial begin
+    dev_adr = 7'h1c;
+    ack = 'b1;
+    tx_byte = 'h00;
+    fan_status  = 'hCA;
+    temp_status = 'hFE;
+    volt_status = 'hBE;
+    fan_speed = '{'h01, 'h02, 'h03, 'h04, 'h05, 'h06, 'h07, 'h08, 'h09, 'h0A,
+    'h0B, 'h0C};
+    temps = '{'h11, 'h12, 'h13, 'h14, 'h15, 'h16};
+  end
+
+  task new_values;
+  
+    randomize (fan_status);
+    randomize (temp_status);
+    randomize (volt_status);
+    randomize (fan_speed);
+    randomize (temps);
+
+  endtask : new_values
+
+  // main functionality of FCM2, provide apropriate data depending on requested
+  // command
+  task reply;
+
+    int cmd;
+
+    $display("Execute reply");
+    // react only on proper address
+    wait(adr_good_p)
+    @(posedge clk_i);
+    // get command index
+    wait(r_done)
+    @(posedge clk_i);
+    cmd = rx_byte;
+
+    case(cmd)
+      0: begin
+        $display("Providing data for cmd0");
+        tx_byte <= fan_status;
+      end
+
+      1: begin
+        $display("Providing data for cmd1");
+        tx_byte <= temp_status;
+      end
+
+      2: begin
+        $display("Providing data for cmd2");
+        tx_byte <= volt_status;
+      end
+
+      3: begin
+        $display("Providing data for cmd3");
+        for (int i=0; i<12; i++) begin
+          tx_byte <= fan_speed[i];
+          @(posedge w_done);
+        end
+        $display("Done");
+      end
+
+      4: begin
+        $display("Providing data for cmd4");
+        for (int i=0; i<6; i++) begin
+          tx_byte <= temps[i];
+          @(posedge w_done);
+        end
+        $display("Done");
+      end
+
+    endcase
+    
+  endtask : reply
+
+endinterface
--- a/hdl/sim/include/Manifest.py
+++ b/hdl/sim/include/Manifest.py
 files = [ "logger.svh", "masterfip-common.svh", "mock_turtle_driver.svh",
        "mt_cpu_csr_driver.svh", "mt_mqueue_host_driver.svh",
        "serializable.svh", "vhd_wishbone_master.svh", "wrn_cpu_csr_regs.vh" ]
+
+include_dirs = [ "wb" ]
--- a/hdl/syn/gefe_test.tcl
+++ b/hdl/syn/gefe_test.tcl
@@ -11,8 +11,12 @@ create_links \
         -hdl_source {../top/gefe_test/gefe_top.vhd} \
         -hdl_source {../rtl/wic_modules/wic_pkg.vhd} \
         -hdl_source {../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd} \
+         -hdl_source {../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd} \
+         -hdl_source {../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd} \
         -hdl_source {../rtl/wic_modules/wic_main.vhd} \
-         -hdl_source {../rtl/wic_modules/wic_simulator.vhd}
+         -hdl_source {../rtl/wic_modules/wic_simulator.vhd} \
+         -hdl_source {../rtl/diot_diag/diag_pkg.vhd} \
+         -hdl_source {../rtl/diot_diag/diot_diag.vhd}
 import_files \
         -convert_EDN_to_HDL 0 
 create_links \

--- a/hdl/syn/spec_test/Makefile
+++ b/hdl/syn/spec_test/Makefile
--- a/hdl/syn/spec_test/Manifest.py
+++ b/hdl/syn/spec_test/Manifest.py
@@ -11,4 +11,5 @@ syn_project = "spec_top.xise"
 top_module = "spec_top"
 syn_tool = "ise"

-modules = { "local" : [ "../../rtl", "../../top/spec_test", "../../ip_cores/nanofip-gateware/top" ] }
+modules = { "local" : [ "../../rtl", "../../top/spec_test",
+    "../../ip_cores/nanofip-gateware/top", "../../ip_cores/general-cores"] }
--- a/hdl/syn/spec_test/spec_top.xise
+++ b/hdl/syn/spec_test/spec_top.xise
--- a/hdl/testbench/spec_test/Manifest.py
+++ b/hdl/testbench/spec_test/Manifest.py
@@ -3,7 +3,7 @@ sim_tool = "modelsim"
 top_module = "main"

 vcom_opt = "-2008 -mixedsvvh l"
-vlog_opt = "+incdir+../../ip_cores/masterfip-gw/testbench/top_mt"
+vlog_opt = "+incdir+../../ip_cores/masterfip-gw/testbench/top_mt +incdir+../../sim"

 # create a fake proasic3 library needed by nanofip
 sim_pre_cmd = "vlib ../fake_proasic3; vmap proasic3 ../fake_proasic3"
@@ -13,7 +13,7 @@ files = ["sim_main.sv", "ram4k9.v" ]
 include_dirs = [ "../../sim", "../../sim/include", "../../sim/include/wb" ]

 modules = {
-        "local" : ["../../rtl", "../../top/spec_test",
+        "local" : ["../../sim/fcm2", "../../rtl", "../../top/spec_test",
        "../../ip_cores/nanofip-gateware/top",
        "../../ip_cores/general-cores/"]}
 #, "../../ip_cores/masterfip-gw/testbench/top_mt"]}
--- a/hdl/testbench/spec_test/run.do
+++ b/hdl/testbench/spec_test/run.do
-vsim work.main
+vsim -L unisim work.main -voptargs="+acc"
 do wave.do
-run -all
+run 12ms
+#run -all
+wave zoomfull
--- a/hdl/testbench/spec_test/sim_main.sv
+++ b/hdl/testbench/spec_test/sim_main.sv
@@ -60,6 +60,7 @@ module main;

  reg [7:0] nf_address = 8'h01;  // Substation data
  wire [2:0] nf_p3lgth;
+  tri1 diag_scl, diag_sda;

  // power-on-reset
  reg rstpo_n = 0;
@@ -91,7 +92,10 @@ module main;
    .var2_rdy_i (nf_var2_rdy),
    .var1_acc_o (nf_var1_acc),
    .var1_rdy_i (nf_var1_rdy),
-    .p3_lgth_o  (nf_p3lgth));
+    .p3_lgth_o  (nf_p3lgth),
+  
+    .diag_scl_b (diag_scl),
+    .diag_sda_b (diag_sda));

  //------------------------------------------------
  nanofip NF(
@@ -151,6 +155,11 @@ module main;
    .jc_tdo_i(1'b0)
 );

+  pentair_fcm2_model sim_FCM2(
+    .clk_i(wclk),
+    .rst_n_i(rstpo_n),
+    .sda_b(diag_sda),
+    .scl_b(diag_scl));

 //------------------------------------------------
 //      HERER we start sending/receiving stuff
@@ -158,6 +167,7 @@ module main;
  initial begin
    FipFrame fip_frame;
    uint8_t payload[0:123] = '{124{'h00}};
+    uint16_t tmp;
  
    fieldrive.speed = 'h01;  //1Mbps
    fip_master.setSpeed(1000000);
@@ -166,25 +176,25 @@ module main;
    #10us;      // wait for reset

    // program WorldFIP cycle for tests
-    for (int i = 0; i < 10; i++) begin
-      $display("Cycle ", i);
-      payload[0:123] = '{124{'h00}};
-      payload[i] = 'h01;
-      fip_frame = FipFrame::makeMF_ID_DAT('h05, nf_address);
-      fip_master.sendFrame(fip_frame);
-      #50us;      // silence time
-
-      // sending VAR1 to be consumed
-      fip_frame = FipFrame::makeMF_RP_DAT(payload);
-      fip_master.sendFrame(fip_frame);
-      #100us;      // silence time
-
-      // getting VAR3 produced by nanoFIP
-      fip_frame = FipFrame::makeMF_ID_DAT('h06, nf_address);
-      fip_master.sendFrame(fip_frame);
-
-      #5ms;      // silence time
-    end
+    payload[0:123] = '{124{'h00}};
+      for (int i = 0; i < 8; i++) begin
+        $display("Cycle ", i);
+        payload[4] = 1 << i;
+        fip_frame = FipFrame::makeMF_ID_DAT('h05, nf_address);
+        fip_master.sendFrame(fip_frame);
+        #50us;      // silence time
+
+        // sending VAR1 to be consumed
+        fip_frame = FipFrame::makeMF_RP_DAT(payload);
+        fip_master.sendFrame(fip_frame);
+        #100us;      // silence time
+
+        // getting VAR3 produced by nanoFIP
+        fip_frame = FipFrame::makeMF_ID_DAT('h06, nf_address);
+        fip_master.sendFrame(fip_frame);
+
+        #5ms;      // silence time
+      end

    $stop();
  end

--- a/hdl/testbench/spec_test/wave.do
+++ b/hdl/testbench/spec_test/wave.do
--- a/hdl/top/gefe_test/gefe_top.pdc
+++ b/hdl/top/gefe_test/gefe_top.pdc
@@ -58,6 +58,10 @@ set_io {leds_o[4]}    -pinname AF2 -fixed YES -iostd LVCMOS25 -register NO -res_
 set_io {leds_o[5]}    -pinname AE1 -fixed YES -iostd LVCMOS25 -register NO -res_pull NONE

 ### Backplane I/O assignments
+set_io {diag_scl_b}   -pinname J15  -fixed YES -iostd LVCMOS25
+set_io {diag_sda_b}   -pinname E14  -fixed YES -iostd LVCMOS25
+
+
 #set_io {s1_p_b[0]}    -pinname F20  -fixed YES -iostd LVCMOS25 -register NO -res_pull NONE
 #set_io {s1_n_b[0]}    -pinname E20  -fixed YES -iostd LVCMOS25 -register NO -res_pull NONE
 #set_io {s1_p_b[1]}    -pinname A27  -fixed YES -iostd LVCMOS25 -register NO -res_pull NONE

--- a/hdl/top/gefe_test/gefe_top.vhd
+++ b/hdl/top/gefe_test/gefe_top.vhd
@@ -32,6 +32,7 @@ use ieee.std_logic_1164.all;
 use ieee.std_logic_misc.all;
 use ieee.numeric_std.all;
 use work.wic_pkg.all;
+use work.diag_pkg.all;

 library unisim;
 use unisim.vcomponents.all;
@@ -63,8 +64,9 @@ entity gefe_top is

    -- backplane connections
    -- in the first HW demonstrator not all slots are fully populated
--    i2c_scl_o  : out   std_logic;
--    i2c_sda_b  : inout std_logic;
+    -- crate monitoring
+    diag_scl_b  : inout std_logic;
+    diag_sda_b  : inout std_logic;
 --
 --    shared_bus : inout std_logic_vector(3 downto 0);
 --    irq_n_i    : in  std_logic;
@@ -104,8 +106,12 @@ architecture rtl of gefe_top is
  signal leds      : std_logic_vector(5 downto 0);
  signal rst_cnt   : unsigned(5 downto 0) := (others=> '0');
  signal rst_n     : std_logic;
+  signal scl_out, sda_out  : std_logic;
+  signal scl_oen, sda_oen  : std_logic;
+
  signal slots_in  : t_wic_slot_in_array(c_SLOT_NUM-1 downto 0);
  signal slots_out : t_wic_slot_out_array(c_SLOT_NUM-1 downto 0);
+  signal diags     : t_diag_out;

 begin

@@ -135,6 +141,8 @@ begin
    slots_i    => slots_in,
    slots_o    => slots_out,

+    diags_i    => diags,
+
    wb_cyc_o   => cyc_o,
    wb_stb_o   => stb_o,
    wb_we_o    => we_o,
@@ -154,6 +162,23 @@ begin
    var1_rdy_i => var1_rdy_i,
    p3_lgth_o  => p3_lgth_o);

+-------------------------------------------------------------------------------
+  
+  cmp_diot_diag: entity work.diot_diag
+  port map(
+    rst_n_i => rst_n,
+    clk_i   => clk_25m_i,
+    scl_o   => scl_out,
+    scl_oen => scl_oen,
+    scl_i   => diag_scl_b,
+    sda_o   => sda_out,
+    sda_oen => sda_oen,
+    sda_i   => diag_sda_b,
+    diags_o => diags);
+
+  diag_scl_b <= scl_out when scl_oen = '0' else 'Z';
+  diag_sda_b <= sda_out when sda_oen = '0' else 'Z';
+
 -------------------------------------------------------------------------------

 GEN_IO_EMULATOR: if c_IO_EMULATION = true generate

--- a/hdl/top/spec_test/spec_top.vhd
+++ b/hdl/top/spec_test/spec_top.vhd
@@ -32,6 +32,7 @@ use ieee.std_logic_1164.all;
 use ieee.std_logic_misc.all;
 use ieee.numeric_std.all;
 use work.wic_pkg.all;
+use work.diag_pkg.all;

 library unisim;
 use unisim.vcomponents.all;
@@ -60,7 +61,11 @@ entity spec_top is
    var2_rdy_i : in  std_logic;
    var1_acc_o : out std_logic;
    var1_rdy_i : in  std_logic;
-    p3_lgth_o  : out std_logic_vector(2 downto 0)
+    p3_lgth_o  : out std_logic_vector(2 downto 0);
+
+    -- crate monitoring
+    diag_scl_b : inout std_logic := '1';
+    diag_sda_b : inout std_logic := '1'
  );
 end spec_top;

@@ -78,9 +83,12 @@ architecture rtl of spec_top is
  signal clk_sys_25m_n     : std_logic;
  signal clk_sys_locked    : std_logic;
  signal rst_n             : std_logic;
+  signal scl_out, sda_out  : std_logic;
+  signal scl_oen, sda_oen  : std_logic;

  signal slots_in  : t_wic_slot_in_array(c_SLOT_NUM-1 downto 0);
  signal slots_out : t_wic_slot_out_array(c_SLOT_NUM-1 downto 0);
+  signal diags     : t_diag_out;

 begin

@@ -173,6 +181,8 @@ begin
    slots_i    => slots_in,
    slots_o    => slots_out,

+    diags_i    => diags,
+
    wb_cyc_o   => cyc_o,
    wb_stb_o   => stb_o,
    wb_we_o    => we_o,
@@ -192,6 +202,23 @@ begin
    var1_rdy_i => var1_rdy_i,
    p3_lgth_o  => p3_lgth_o);

+-------------------------------------------------------------------------------
+  
+  cmp_diot_diag: entity work.diot_diag
+  port map(
+    rst_n_i => rst_n,
+    clk_i   => clk_sys_25m,
+    scl_o   => scl_out,
+    scl_oen => scl_oen,
+    scl_i   => diag_scl_b,
+    sda_o   => sda_out,
+    sda_oen => sda_oen,
+    sda_i   => diag_sda_b,
+    diags_o => diags);
+
+  diag_scl_b <= scl_out when scl_oen = '0' else 'Z';
+  diag_sda_b <= sda_out when sda_oen = '0' else 'Z';
+
 -------------------------------------------------------------------------------

  GEN_SIMULATOR: for I in 0 to c_SLOT_NUM-1 generate