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DIOT Zynq Ultrascale-based System Board
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DIOT Zynq Ultrascale-based System Board
Issues
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[General] use multi-diode chip PESD3V3L4UG if possible
#9
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Minor
sch-v1
CLOSED
9
updated
Apr 06, 2020
[General] cleanup schematics
#8
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Minor
sch-v1
CLOSED
7
updated
Apr 06, 2020
[General] use "_N" suffix for all negative signals (instead of "#")
#7
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Minor
sch-v1
CLOSED
1
updated
Mar 06, 2020
[General] naming of backplane signals shared between slots
6 of 6 tasks completed
#6
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Minor
sch-v1
CLOSED
3
updated
Mar 30, 2020
[General] Two Altium variants of this design
#5
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Major
sch-v1
CLOSED
9
updated
Mar 30, 2020
[General] Xilinx BGA package delays
#4
· opened
Jan 27, 2020
by
Grzegorz Daniluk
layout-v1.0
Done
Major
CLOSED
10
updated
Sep 03, 2020
[General] Double SFP cage
#3
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Major
sch-v1
CLOSED
2
updated
Mar 06, 2020
[General] PRTR5V0U2X has designator D* in most places except for IC4.
#2
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Major
sch-v1
CLOSED
1
updated
Mar 06, 2020
[General] swapped sheets with FPGA banks 63/64
#1
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Major
sch-v1
CLOSED
1
updated
Mar 06, 2020
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