* Si5341A 100 Hz to 1.028 GHz Integer (< 100 fs) and fractional (< 150 fs)
* Si5341B 100 Hz to 350 MHz "
* Si5341C 100 Hz to 1.028 GHz Integer only (< 100 fs)
* Si5341D* 100 Hz to 350 MHz "
*
* * Based on your calculated frequency plan, a Si5341D grade device is
* sufficient for your design. For more in-system configuration flexibility
* (higher frequencies and/or to enable fractional synthesis), consider
* selecting device grade Si5341A when specifying an ordering part number (OPN)
* for your application. See the datasheet Ordering Guide for more information.
*
* Design
* ======
* Host Interface:
* I/O Power Supply: VDDA (3.3V)
* SPI Mode: 4-Wire
* I2C Address Range: 116d to 119d / 0x74 to 0x77 (selected via A0/A1 pins)
*
* Inputs:
* XAXB: Unused
* IN0: 25 MHz
* Standard
* IN1: Unused
* IN2: Unused
* FB_IN: 25 MHz
* Standard
*
* Outputs:
* OUT0: 125 MHz
* Enabled, LVDS 1.8 V
* OUT1: 156.25 MHz
* Enabled, LVDS 1.8 V
* OUT2: 125 MHz
* Enabled, LVDS 1.8 V
* OUT3: 125 MHz
* Enabled, LVDS 1.8 V
* OUT4: 125 MHz
* Enabled, LVDS 1.8 V
* OUT5: 125 MHz
* Enabled, LVDS 1.8 V
* OUT6: 62.5 MHz
* Enabled, LVDS 1.8 V
* OUT7: 125 MHz
* Enabled, LVDS 1.8 V
* OUT8: 125 MHz
* Enabled, LVDS 1.8 V
* OUT9: ZDM - 25 MHz
* Enabled, LVDS 1.8 V
*
* Frequency Plan
* ==============
* Priority: maximize the number of low jitter outputs
*
* Fpfd = 25 MHz
* Fvco = 13.75 GHz
* Fms0 = 1.25 GHz
*
* P dividers:
* P0 = 1
* P1 = Unused
* P2 = Unused
* P3 = 1
* Pxaxb = Unused
*
* M = 550
* N dividers:
* N0 (Zero Delay):
* Value: 11
* OUT0: 125 MHz
* OUT1: 156.25 MHz [ 156 + 1/4 MHz ]
* OUT2: 125 MHz
* OUT3: 125 MHz
* OUT4: 125 MHz
* OUT5: 125 MHz
* OUT6: 62.5 MHz [ 62 + 1/2 MHz ]
* OUT7: 125 MHz
* OUT8: 125 MHz
* OUT9: 25 MHz
* N1:
* Unused
* N2:
* Unused
* N3:
* Unused
* N4:
* Unused
*
* R dividers:
* R0 = 10
* R1 = 8
* R2 = 10
* R3 = 10
* R4 = 10
* R5 = 10
* R6 = 20
* R7 = 10
* R8 = 10
* R9 = 50
*
* Dividers listed above show effective values. These values are translated to register settings by ClockBuilder Pro. For the actual register values, see below. Refer to the Family Reference Manual for information on registers related to frequency plan.
*
* Digitally Controlled Oscillator (DCO)
* =====================================
* Mode: Register Direct Write
*
* N0: DCO Disabled
*
* N1: DCO Disabled
*
* N2: DCO Disabled
*
* N3: DCO Disabled
*
* N4: DCO Disabled
*
* Estimated Power & Junction Temperature
* ======================================
* Assumptions:
*
* Revision: D
* VDD: 1.8 V
* Ta: 25 C
* Theta-JA: 18.3 C/W
* Airflow: 2 m/s
*
* Total Power: 897 mW, On Chip Power: 837 mW, Tj: 40 C
*
* Frequency Format Voltage Current Power
* ---------- ------ -------- -------- --------
* VDD 1.8 V 135.1 mA 243 mW
* VDDA 3.3 V 113.7 mA 375 mW
* VDDO0 125 MHz LVDS 1.8 V 15.6 mA 28 mW
* VDDO1 156.25 MHz LVDS 1.8 V 15.7 mA 28 mW
* VDDO2 125 MHz LVDS 1.8 V 15.6 mA 28 mW
* VDDO3 125 MHz LVDS 1.8 V 15.6 mA 28 mW
* VDDO4 125 MHz LVDS 1.8 V 15.6 mA 28 mW
* VDDO5 125 MHz LVDS 1.8 V 15.6 mA 28 mW
* VDDO6 62.5 MHz LVDS 1.8 V 15.3 mA 28 mW
* VDDO7 125 MHz LVDS 1.8 V 15.6 mA 28 mW
* VDDO8 125 MHz LVDS 1.8 V 15.6 mA 28 mW
* VDDO9 25 MHz LVDS 1.8 V 15.1 mA 27 mW
* -------- --------
* Total 403.9 mA 897 mW
*
* Note:
*
* -Tj is junction temperature. Tj must be less than 125 C (on Si5341 Revision D) for device to comply with datasheet specifications. Tj = Ta + Theta_JA*On_Chip_Power.
* -Overall power includes on-chip power dissipation and adds differential load power dissipation to estimate total power requirements.
* -Above are estimates only: power and temperature should be measured on your PCB.
* -Selection of appropriate Theta-JA is required for most accurate estimate. Ideally, select 'User Specified Theta-JA' and enter a Theta-JA value based on the thermal properties of your PCB.
