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## Project description
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## Project description
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The DI/OT System Board is one of the main components of the [Distributed I/O Tier project ecosystem](https://ohwr.org/project/diot/wikis/home). It is designed in compliance with the Compact PCI Serial standard (CPCI-S.0) and therefore can act as a System Board in off-the-shelf CompactPCI-Serial crates.
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The DI/OT System Board is one of the main components of the [Distributed I/O Tier project ecosystem](https://ohwr.org/project/diot/wikis/home). It is mechanically and electrically compliant with the Compact PCI Serial standard (CPCI-S.0).
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The DI/OT System Board controls the whole DI/OT crate, communicating with up to 8 Peripheral Boards and higher layers of the control system using [White Rabbit](https://ohwr.org/project/white-rabbit/wikis/home), Gigabit Ethernet or any other industrial fieldbus.
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The DI/OT System Board controls the whole DI/OT crate, communicating with up to 8 Peripheral Boards and higher layers of the control system using [White Rabbit](https://ohwr.org/project/white-rabbit/wikis/home), Gigabit Ethernet or any other industrial fieldbus.
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| PL DDR4 8Gb | MT40A512M16LY-075:E | 1 | | 8Gb (512M x 16 x 4) |
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| PL DDR4 8Gb | MT40A512M16LY-075:E | 1 | | 8Gb (512M x 16 x 4) |
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| QSPI 512Mbit | MT25QU512ABB | 2 | 7S, ZCU102 | NOR Flash. Xilinx recommends QSPI32 for flash size larger than 16MB (UG1085 v1.9 p233)|
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| QSPI 512Mbit | MT25QU512ABB | 2 | 7S, ZCU102 | NOR Flash. Xilinx recommends QSPI32 for flash size larger than 16MB (UG1085 v1.9 p233)|
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| eMMC 32Gb | IS21ES04G-JCLI | 1 | 7S | 4Gb x 8 |
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| eMMC 32Gb | IS21ES04G-JCLI | 1 | 7S | 4Gb x 8 |
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| micro-SD | | 1 | | To simplify board bring-up, later not mounted since eMMC will be used for filesystem. |
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### White Rabbit support
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### White Rabbit support
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*See SPEC sch (page 2, 16) and FASEC sch (page 22) for reference*
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*See SPEC sch (page 2, 16) and FASEC sch (page 22) for reference*
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| ------ | ------ | ------ | ------ | ------ |
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| ------ | ------ | ------ | ------ | ------ |
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| PS REF CLK | 48 MHz | 1 | AFCZ | anything between 27MHz-60MHz (DS925, p.32) |
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| PS REF CLK | 48 MHz | 1 | AFCZ | anything between 27MHz-60MHz (DS925, p.32) |
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| PS RTC crystal | 32.768 kHz | 1 | ZCU102, AFCZ | DS925 p.33 |
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| PS RTC crystal | 32.768 kHz | 1 | ZCU102, AFCZ | DS925 p.33 |
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| ?? Clock cross-point switch | IDT 8V54816A | 1 | AFCZ | Clock distribution: WR ref clock, programmable out from AD9516/Si5341, ZU7, 8 Peripheral Slots (n_PE_CLK); 86 CHF per chip!!; TODO: discuss clock distribution network |
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| ?? Clock cross-point switch | | 1 | | Clock distribution: WR ref clock, programmable out from AD9516/Si5341, ZU7, 8 Peripheral Slots (n_PE_CLK); 86 CHF per chip!!; TODO: discuss clock distribution network |
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| | | | | Alternatively, input all clocks to FPGA and decide there on crossing/switching. TODO: measure how much jitter adds Ultrascale+ family |
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| | | | | Alternatively, input all clocks to FPGA and decide there on crossing/switching. TODO: measure how much jitter adds Ultrascale+ family |
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### Power
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### Power
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| **Type** | **Component** | **How many** | **Other designs** | **Comments** |
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| **Type** | **Component** | **How many** | **Other designs** | **Comments** |
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| ------ | ------ | ------ | ------ | ------ |
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| ------ | ------ | ------ | ------ | ------ |
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| Multi-level solution | MAX77714 | | | [Maxim power solutions for Xilinx](https://www.maximintegrated.com/en/products/power/switching-regulators/applications/fpga-power/xilinx-fpga-power-solutions/power-solutions-for-xilinx-artix-spartan-and-zynq-fpgas.html/tb_order) |
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| Multi-level solution | ??? | | | [Maxim power solutions for Xilinx](https://www.maximintegrated.com/en/products/power/switching-regulators/applications/fpga-power/xilinx-fpga-power-solutions/power-solutions-for-xilinx-artix-spartan-and-zynq-fpgas.html/tb_order),<br> [Infineon](https://www.infineon.com/cms/en/product/promopages/xilinx-SoC-FPGA-power-reference-design/All-of-Infineons-Zynq-UltraScale-MPSoC-Power-Macros/) |
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### Miscellaneous
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### Miscellaneous
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| **Type** | **Component** | **How many** | **Other designs** | **Comments** |
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| **Type** | **Component** | **How many** | **Other designs** | **Comments** |
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| ------ | ------ | ------ | ------ | ------ |
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| ------ | ------ | ------ | ------ | ------ |
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| 12V, GND headers pads | -- | 1 | -- | For external powering during first tests |
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| 12V aux power connector | 4-pin Molex | 1 | -- | For external powering during first tests |
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| Xilinx JTAG connector | MOLEX 87832-1420 | 1 | -- | |
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| Xilinx JTAG connector | MOLEX 87832-1420 | 1 | -- | |
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| Self power-cycle circuit driving backplane PS_ON# | | 1 | | In normal operation PS_ON# has to be grounded, if driven high or open-circuited PSU shuts off 12V rail |
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| Self power-cycle circuit driving backplane PS_ON# | | 1 | | In normal operation PS_ON# has to be grounded, if driven high or open-circuited PSU shuts off 12V rail |
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| External watchdog chip for PL | LTC2917HMS-B1#PBF | 1 | FASEC |
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| External watchdog chip for PL | LTC2917HMS-B1#PBF | 1 | FASEC |
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| Thermometers | | 3? | | |
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| Thermometers | | 3? | | |
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| 12V header connector for FPGA fan | | 1 | +12V PWM-driven from FPGA, with tachometer pin |
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| 12V header connector for FPGA fan | | 1 | +12V PWM-driven from FPGA, with tachometer pin |
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| FPGA fan control and monitoring | MAX6639AEE+ | | 1 | Provides SMBus interface |
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| Mounting holes for FPGA heatsink | | | |
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| Mounting holes for FPGA heatsink | | | |
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| USB UART | | 1 | | |
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| USB UART | | 1 | | |
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