... | ... | @@ -40,8 +40,8 @@ The DI/OT System Board controls the whole DI/OT crate, communicating with up to |
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| Startup OSC | FNETHE025 | 1 | WRS | |
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| I2C EEPROM | 24AA64T-I/MC | 1 | FASEC, HT FMC mezzanines | for WRPC configuration |
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| I2C Unique ID | 24AA025E48 | 1 | SPEC7 | on the same I2C bus with EEPROM |
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| 1-PPS OUT buffers | SN74LVT125DW | 3 | WRS | see SCB v3.4 (page 3) for reference, pin header with 1-PPS and Abscal |
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| ABSCAL OUT buffers | SN74LVT125DW | 3 | WRS | see SCB v3.4 (page 3) for reference, pin header with 1-PPS and Abscal |
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| 1-PPS OUT buffers | SN74LVT125DW | 3 | WRS | see SCB v3.4 (page 3) for reference, pin header with 1-PPS and Abscal<br> Will be used for WR calibration. |
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| ABSCAL OUT buffers | SN74LVT125DW | 3 | WRS | see SCB v3.4 (page 3) for reference, pin header with 1-PPS and Abscal<br> Will be used for WR calibration. |
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### Other oscillators / clock generators
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... | ... | @@ -97,9 +97,9 @@ The DI/OT System Board controls the whole DI/OT crate, communicating with up to |
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* I2C SCL and SDA (P1.B2; P1.C2) shall be pulled-up to 3.3V
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* PS_ON# (P1.E2) shall be connected to an external watchdog/self-reset circuit for remote power-cycling the whole crate
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* RST# (P1.F2), WAKE_IN# (P1.I2) pulled-up to 3.3V
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* PRST# (P1.H2) - ESD-protected through I/O buffer / TVS diode
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* PWRBTN# (P1.C3) - ESD-protected through I/O buffer / TVS diode
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* Monitoring I/Os (PS_ON#, PWRFAIL, P_PRES, M_SDA, M_SCL, P_RST, P_IO0-2, F_RST, F_IO0-1) - ESD-protected through I/O buffer / TVS diode
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* PRST# (P1.H2) - ESD-protected through 3.3V TVS diode
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* PWRBTN# (P1.C3) - ESD-protected through 3.3V TVS diode
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* Monitoring I/Os (PS_ON#, PWRFAIL, P_PRES, M_SDA, M_SCL, P_RST, P_IO0-2, F_RST, F_IO0-1) - ESD-protected through 3.3V TVS diode
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* P_PRES0, P_PRES1, M_SDA, M_SCL pulled-up to 3.3V
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* SATA_SDI, SATA_SDO, SATA_SL, SATA_SCL - shall be pulled-up to 3.3V
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