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GW: add Chip2Chip/Aurora link subsystem to all peripheral boards

Adrian Byszuk requested to merge gw_add_gbit_links into master

This MR adds fully functional AXI Chip2Chip/Aurora gigabit link subsystem allowing for easy connectivity with peripheral boards.

  1. Aurora 8b/10b version is used
    6.25 Gbps speed with a standard 125 MHz reference clock.
    This version of Aurora allows reaching only lower link speeds, up to 6.6 Gbps.
    Therefore it could make more sense to use 64b/66b version, but that comes with a few problems.
    The main problem is that 64b/66b version works only with speeds higher than 6.6 Gbps and requires per-quad QPLL, in contrast to per-channel CPLL of 8b/10b version.
    This is problematic because each instance of Aurora 64b/66b IP wants to have control over common QPLL to reset it etc. It's possible to workaround this, but that's left as a future improvement.

  2. Chip2Chip is set as master
    Chip2Chip is configured as master, without a secondary AXI-Lite channel.
    This means that the SB is the DMA master. Possibly in the future this will be inverted - peripheral board will be the master, and Chip2Chip will have enabled auxiliary, reverse AXI-Lite channel for SB->PB access.

  3. All peripheral boards available under separate 32 bit address spaces
    Access is possible either directly from PS, or through a CDMA engine in the PL.

  4. AXI ID width explicitly cut down on PS -> Chip2Chip crossbar
    A bit peculiar and undocumented thing about Chip2Chip is that it uses a hidden, complex formula to determine minimum number of serial lanes required for a link.
    This formula takes into account widths of all the AXI bus fields (ID, w_addr, r_addr, data, user, strb, qos etc.).
    Because AXI bus coming out of PS has ID width = 16, this already forces Chip2Chip to require 2 serial lanes per link, which is impossible in DIOT.
    The only way to solve this in BD is to configure the crossbar between PS and Chip2Chip cores to "shared" SASD mode, which basically serializes all requests and trims ID width to 0 (and now C2C can be satisfied with only one lane).
    This may of course influence performance as we lose all possible parallelism. On the other hand, there won't be any parallelism wrt. AXI requests coming from PS, so maybe it's not that big of a deal.

Edited by Alén Arias Vázquez

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