Skip to content
GitLab
Explore
Sign in
Projects
DIOT Zynq Ultrascale-based System Board
Issues
#98
[fpga-bank-27-28] remove FMC.CLK_DIR and FMC.CLK_BIDIR_2/3
remove FMC.CLK_DIR and FMC.CLK_BIDIR_2/3 (see also issues
#35 (closed)
,
#36 (closed)
)
Edited
Jan 27, 2020
by
Grzegorz Daniluk
To upload designs, you'll need to enable LFS and have an admin enable hashed storage.
More information