[fpga-config] Power IC27 from P5VREG (see screenshot)
While keeping P3V3 pull-ups for resistor divider and reset signals. We need to ensure that these resets are pulled down when the various FPGA voltage levels are sequenced. In the same time, it needs to work if we reset 12V in the backplane (5V is always on).
![2020-01-27-155809_895x510_scrot](data:image/gif;base64,R0lGODlhAQABAAAAACH5BAEKAAEALAAAAAABAAEAAAICTAEAOw==)