[clocks] FPGA_CLK_OUT AC coupling and termination
Shouldn't FPGA_CLK_OUT be AC coupled before it goes to Si5341? - check input levels of the chip, FPGA clk comes from 3.3V bank. Do we need to provide bias resistor network?
FPGA_CLK_OUT misses 100Ohm termination (see SI5341 rev D datasheet section 3.3.2 Input Clocks (IN0, IN1, IN2)