IC20 +3V3 instead of +3V3_CLK
IC20 is powered from the 3v3_CLK, it's inputs are from SoC bank 94 which is powered by +3V3.
This "high" 2 x ~50mA current switching when the output has a 30R load connected will effect P3V3_CLK.
Also not clear the note on phase delay implies moving in close proximity to SoC, perhaps this meant as a differential length constraint to be applied to these signals instead, or if this is truly dependent on delays, it should be a pair of differential sigansl with controlled impedance.