FPGA_Banks_6_7: connecting FMC clocks
If CCC_SW1_CLK_I1/CCC_SW_0_CLKI1 can be only single-ended (is it 100% true?). Then maybe worth adding external LVDS buffer right next the FPGA so that the clock signal can be fed differentially from FMC and translated to single-ended right before it enters the FPGA pin. E.g. SN65LVDS2 was qualified in radiation.