FPGA_Bank1 cannot be used with LVDS signals, only single-ended or SSTL
Which is the reason why I'd not use ot for FMC LA diff pairs. Unless there is a good reason for it?
I'd rather use Bank1 for signals that are anyway single-ended (and only a few FMC LAs) and split FMC LA through several I/O banks. See below the initial I/O planning we did some time ago: