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DIOT Kintex Ultrascale-based Peripheral Board FMC Carrier
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DIOT Kintex Ultrascale-based Peripheral Board FMC Carrier
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FPGA_Bank_44-46_48_FMC: Verify schematics note
#99
· opened
Sep 08, 2021
by
Grzegorz Daniluk
layout-v1.0
Done
minor
CLOSED
1
updated
Sep 16, 2021
Silkscreen: add hyperlinks
#98
· opened
Sep 08, 2021
by
Grzegorz Daniluk
layout-v1.0
Done
minor
CLOSED
0
updated
Sep 16, 2021
Remove 2 unnecessary mounting holes
#97
· opened
Sep 08, 2021
by
Grzegorz Daniluk
layout-v1.0
Done
minor
CLOSED
0
updated
Sep 16, 2021
L12: P1V8_FMC polygon could be extended to fully cover also the last via
#90
· opened
Jul 21, 2021
by
Grzegorz Daniluk
layout-v1.0
Done
minor
CLOSED
0
updated
Sep 06, 2021
L8: STRIP1 polygon accidentally cut with keep-out layer
#88
· opened
Jul 21, 2021
by
Grzegorz Daniluk
layout-v1.0
Done
minor
CLOSED
0
updated
Sep 06, 2021
L3: effective width of FMC_VREFA_M2C and FMC_VREFB_M2C polygons
#83
· opened
Jul 20, 2021
by
Grzegorz Daniluk
layout-v1.0
Done
minor
CLOSED
2
updated
Sep 07, 2021
L12: add thermal pads (GND) for IRPS5401 (IC21, IC22)
#82
· opened
Jul 20, 2021
by
Grzegorz Daniluk
layout-v1.0
Done
minor
CLOSED
0
updated
Sep 06, 2021
Missing table with layers stackup and total board thickness
#81
· opened
Jul 20, 2021
by
Grzegorz Daniluk
layout-v1.0
minor
CLOSED
2
updated
Jul 21, 2021
Acid traps
3 of 3 tasks completed
#79
· opened
Jul 19, 2021
by
Grzegorz Daniluk
layout-v1.0
Done
minor
CLOSED
0
updated
Sep 06, 2021
FPGA_Bank_44_64_65: LED_USER0 could be moved to Bank44
#73
· opened
Jan 28, 2021
by
Grzegorz Daniluk
sch v1.0
Done
minor
CLOSED
0
updated
Feb 04, 2021
Optimise bill-of-materials
10 of 10 tasks completed
#71
· opened
Dec 03, 2020
by
Grzegorz Daniluk
sch v1.0
Done
minor
CLOSED
1
updated
Jan 28, 2021
USB_Quad and Power_Supply_3 could use the same LDO to produce 3V3 from 5V
#68
· opened
Dec 02, 2020
by
Grzegorz Daniluk
sch v1.0
Done
minor
CLOSED
1
updated
Jan 28, 2021
Re-annotate the whole schematics
#67
· opened
Dec 02, 2020
by
Grzegorz Daniluk
sch v1.0
Done
minor
CLOSED
4
updated
Jan 27, 2021
Sensors: why they are powered from P3V3_reg and not from P3V3?
#65
· opened
Dec 02, 2020
by
Grzegorz Daniluk
sch v1.0
Done
minor
CLOSED
3
updated
Jan 27, 2021
Consider adding pin swapping groups to the FPGA
#64
· opened
Nov 26, 2020
by
Christos Gentsos
layout-v1.0
Done
minor
CLOSED
3
updated
Sep 06, 2021
FPGA_BANK_66_67_68_DDR: random indentation of net labels?
#63
· opened
Nov 23, 2020
by
Grzegorz Daniluk
sch v1.0
Done
minor
CLOSED
0
updated
Jan 27, 2021
Remove wires from unused FPGA pins
#62
· opened
Nov 23, 2020
by
Grzegorz Daniluk
layout-v1.0
Done
minor
CLOSED
1
updated
Sep 06, 2021
FPGA_Bank_44_64_65: rename UART signals
2 of 2 tasks completed
#61
· opened
Nov 23, 2020
by
Grzegorz Daniluk
sch v1.0
Done
minor
CLOSED
0
updated
Jan 27, 2021
FPGA_Bank_0_CFG: "Connect RST_N to PROGRAM_B?" note
#59
· opened
Nov 23, 2020
by
Grzegorz Daniluk
sch v1.0
Done
minor
CLOSED
0
updated
Jan 27, 2021
DDR_SODIMM: orientation of pull-up and pull-down banks
#58
· opened
Nov 23, 2020
by
Grzegorz Daniluk
sch v1.0
Done
minor
CLOSED
0
updated
Jan 27, 2021
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