- 29 Jul, 2019 11 commits
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Christos Gentsos authored
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Christos Gentsos authored
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Christos Gentsos authored
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Christos Gentsos authored
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Christos Gentsos authored
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Christos Gentsos authored
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Christos Gentsos authored
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Christos Gentsos authored
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Christos Gentsos authored
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Christos Gentsos authored
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Christos Gentsos authored
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- 25 Jun, 2019 1 commit
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Christos Gentsos authored
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- 24 Jun, 2019 1 commit
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Christos Gentsos authored
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- 20 Jun, 2019 2 commits
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Christos Gentsos authored
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Christos Gentsos authored
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- 11 Jun, 2019 10 commits
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Christos Gentsos authored
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Christos Gentsos authored
Manufacturer: CERN (BE-CO-HT) Product: DIOT monitoring module (monimod) debug bridge
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Christos Gentsos authored
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Christos Gentsos authored
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Christos Gentsos authored
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Christos Gentsos authored
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Christos Gentsos authored
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Christos Gentsos authored
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Christos Gentsos authored
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Christos Gentsos authored
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- 07 Jun, 2019 6 commits
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Christos Gentsos authored
Ah, we had to set the NVM wait state to 1 for >24MHz operation.
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Christos Gentsos authored
The output of the DPLL was below its operational range, it was probably locking to the wrong frequency. Still can't run at 48MHz for some reason.
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Christos Gentsos authored
13.265 times slower, to be exact - something's fishy.
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Christos Gentsos authored
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Christos Gentsos authored
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Christos Gentsos authored
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