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DIOT Monitoring Module
DIOT Monitoring Module
Commit e4ef198e authored by Adam Wujek's avatar Adam Wujek
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main/i2c: allow the clear of TMR_ERROR_CNT only with zero value 

Signed-off-by: 's avatarAdam Wujek <dev_public@wujek.eu>
parent 5281fd9b
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Showing with 22 additions and 3 deletions
doc/source/firmware.rst
View file @ e4ef198e
......@@ -178,7 +178,7 @@ Commands marked with \+ or \* are:
+----------+---------------------+------------------------+----------+-------------------------------------------------------------------------+
| D7 + | UPTIME_SECS_ | Block read | var(1+4) | get the uptime in seconds |
+----------+---------------------+------------------------+----------+-------------------------------------------------------------------------+
| D8 + | TMR_ERROR_CNT_ | Block read | var(1+4) | get TMR error count |
| D8 + | TMR_ERROR_CNT_ | Block write / read | var(1+4) | clear / get TMR error count |
+----------+---------------------+------------------------+----------+-------------------------------------------------------------------------+
| D9 + | USE_PEC_ | Byte write / read | 1 | turn PEC on / off |
+----------+---------------------+------------------------+----------+-------------------------------------------------------------------------+
......@@ -652,7 +652,7 @@ TMR_ERROR_CNT
~~~~~~~~~~~~~
| Command code: **D8**
| Transaction type: **Block read**
| Transaction type: **Block write / read**
| Data length: **var(1+4)**
When software mitigation through COAST is enabled (see
......@@ -660,6 +660,9 @@ When software mitigation through COAST is enabled (see
this command. Setting `TMR Error` bit in STATUS_CML_ clears the value of this
register.
It is possible to clear the TMR Error counter by writing 0's as data to this
register.
The fist byte of the register contains the number of bytes of data.
For this register, its value is fixed to 4.
......
main_fw/src/i2c_impl.c
View file @ e4ef198e
......@@ -51,6 +51,10 @@ static uint8_t status_b;
extern uint8_t status_cml;
static uint8_t status_cml_tmp;
uint32_t temp_tmr_error_cnt;
void get_tmr_error(void);
void set_tmr_error(void);
void accvolt();
void acccurr();
void accpowr();
......@@ -246,7 +250,7 @@ static const cmd_t cmds_cmds[] = (cmd_t[]){
{0xD5, (int8_t *)&cmd_data_lengths[cmd_0xD5], (uint8_t *)&fw_type, &get_fw_type, &boot_new_fw, (fp_t)NULL, QUERY_WR | QUERY_RD, 0},
{0xD6, (int8_t *)&cmd_data_lengths[cmd_0xD6], (uint8_t *)&reset_byte, (fp_t)NULL, &uc_reset, (fp_t)NULL, QUERY_WR, 0},
{0xD7, (int8_t *)&cmd_data_lengths[cmd_0xD7], (uint8_t *)&seconds_up, (fp_t)NULL, (fp_t)NULL, (fp_t)NULL, QUERY_RD | QUERY_FMT_NAN, 0},
{0xD8, (int8_t *)&cmd_data_lengths[cmd_0xD8], (uint8_t *)&TMR_ERROR_CNT, (fp_t)NULL, (fp_t)NULL, (fp_t)NULL, QUERY_WR | QUERY_RD | QUERY_FMT_NAN,0},
{0xD8, (int8_t *)&cmd_data_lengths[cmd_0xD8], (uint8_t *)&temp_tmr_error_cnt, &get_tmr_error, &set_tmr_error, (fp_t)NULL, QUERY_WR | QUERY_RD | QUERY_FMT_NAN,0},
{0xD9, (int8_t *)&cmd_data_lengths[cmd_0xD9], (uint8_t *)&use_pec_tmp, &get_pec, &set_pec, (fp_t)NULL, QUERY_WR | QUERY_RD, 1},
{0xE0, (int8_t *)&cmd_data_lengths[cmd_0xE0], (uint8_t *)&temp_curve_points_data, &get_tc_curve, &set_tc_curve, (fp_t)NULL, QUERY_WR | QUERY_RD | QUERY_FMT_NAN,0},
{0xE1, (int8_t *)&cmd_data_lengths[cmd_0xE1], (uint8_t *)&temp_matrix_row, &get_tc_matrix, &set_tc_matrix, (fp_t)NULL, QUERY_WR | QUERY_RD | QUERY_FMT_NAN,0},
......@@ -383,6 +387,18 @@ void write_status_cml(void)
TMR_ERROR_CNT = 0;
}
void get_tmr_error(void)
{
temp_tmr_error_cnt = TMR_ERROR_CNT;
}
void set_tmr_error(void)
{
/* Clear TMR_ERROR_CNT only if 0's are written */
if (!temp_tmr_error_cnt)
TMR_ERROR_CNT = temp_tmr_error_cnt;
}
#if defined(MMFANT) || defined(MMPROT)
void __xMR fan_config()
......
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