bootloader/atmel_start: fix i2c, change clock from 48MHz to 24MHz and use internal oscillator

Clock is chaned to 24MHz to be the same as in main_fw The real fix is the use of the internal oscillator Signed-off-by: Adam Wujek <dev_public@wujek.eu>

bootloader/atmel_start: fix i2c, change clock from 48MHz to 24MHz and use internal oscillator
Clock is chaned to 24MHz to be the same as in main_fw The real fix is the use of the internal oscillator Signed-off-by: Adam Wujek <dev_public@wujek.eu>
cf1de06a · Adam Wujek · 7b688558 · cf1de06a · cf1de06a · cf1de06a
Commit cf1de06a authored May 16, 2022 by Adam Wujek
4 changed files
--- a/bootloader/atmel_start_prj/atmel_start_config.atstart
+++ b/bootloader/atmel_start_prj/atmel_start_config.atstart
@@ -30,8 +30,8 @@ drivers:
      $input_id: External Crystal Oscillator 0.4-32MHz (XOSC)
      RESERVED_InputFreq: 400000
      RESERVED_InputFreq_id: External Crystal Oscillator 0.4-32MHz (XOSC)
-      _$freq_output_Generic clock generator 0: 48000000
+      _$freq_output_Generic clock generator 0: 24000000
-      _$freq_output_Generic clock generator 1: 32768
+      _$freq_output_Generic clock generator 1: 31250
      _$freq_output_Generic clock generator 2: 48000000
      _$freq_output_Generic clock generator 3: 400000
      _$freq_output_Generic clock generator 4: 400000
@@ -42,7 +42,7 @@ drivers:
      enable_gclk_gen_0__externalclock: 1000000
      enable_gclk_gen_1: true
      enable_gclk_gen_1__externalclock: 1000000
-      enable_gclk_gen_2: true
+      enable_gclk_gen_2: false
      enable_gclk_gen_2__externalclock: 1000000
      enable_gclk_gen_3: true
      enable_gclk_gen_3__externalclock: 1000000
@@ -65,7 +65,7 @@ drivers:
      gclk_arch_gen_1_oe: false
      gclk_arch_gen_1_oov: false
      gclk_arch_gen_2_RUNSTDBY: false
-      gclk_arch_gen_2_enable: true
+      gclk_arch_gen_2_enable: false
      gclk_arch_gen_2_idc: false
      gclk_arch_gen_2_oe: false
      gclk_arch_gen_2_oov: false
@@ -94,12 +94,12 @@ drivers:
      gclk_arch_gen_7_idc: false
      gclk_arch_gen_7_oe: false
      gclk_arch_gen_7_oov: false
-      gclk_gen_0_div: 1
+      gclk_gen_0_div: 2
      gclk_gen_0_div_sel: false
      gclk_gen_0_oscillator: Digital Frequency Locked Loop (DFLL48M)
-      gclk_gen_1_div: 1
+      gclk_gen_1_div: 32
      gclk_gen_1_div_sel: false
-      gclk_gen_1_oscillator: 32kHz External Crystal Oscillator (XOSC32K)
+      gclk_gen_1_oscillator: 8MHz Internal Oscillator (OSC8M)
      gclk_gen_2_div: 1
      gclk_gen_2_div_sel: false
      gclk_gen_2_oscillator: Digital Frequency Locked Loop (DFLL48M)
@@ -128,11 +128,11 @@ drivers:
    functionality: System
    api: HAL:HPL:PM
    configuration:
-      $input: 48000000
+      $input: 24000000
      $input_id: Generic clock generator 0
-      RESERVED_InputFreq: 48000000
+      RESERVED_InputFreq: 24000000
      RESERVED_InputFreq_id: Generic clock generator 0
-      _$freq_output_CPU: 48000000
+      _$freq_output_CPU: 24000000
      apba_div: '1'
      apbb_div: '1'
      apbc_div: '1'
@@ -477,14 +477,14 @@ drivers:
    functionality: System
    api: HAL:HPL:SYSCTRL
    configuration:
-      $input: 32768
+      $input: 31250
      $input_id: Generic clock generator 1
-      RESERVED_InputFreq: 32768
+      RESERVED_InputFreq: 31250
      RESERVED_InputFreq_id: Generic clock generator 1
      _$freq_output_8MHz Internal Oscillator (OSC8M): 1000000
      _$freq_output_Digital Frequency Locked Loop (DFLL48M): 48000000
      _$freq_output_External Crystal Oscillator 0.4-32MHz (XOSC): 400000
-      _$freq_output_Fractional Digital Phase Locked Loop (FDPLL96M): 47998976
+      _$freq_output_Fractional Digital Phase Locked Loop (FDPLL96M): 45775390.625
      dfll48m_arch_bplckc: false
      dfll48m_arch_calibration: false
      dfll48m_arch_ccdis: true
@@ -506,10 +506,10 @@ drivers:
      enable_dfll48m: true
      enable_fdpll96m: false
      enable_osc32k: false
-      enable_osc8m: false
+      enable_osc8m: true
      enable_osculp32k: false
      enable_xosc: false
-      enable_xosc32k: true
+      enable_xosc32k: false
      fdpll96m_arch_enable: false
      fdpll96m_arch_lbypass: true
      fdpll96m_arch_ondemand: false
@@ -528,7 +528,7 @@ drivers:
      osc32k_arch_startup: 3 Clock Cycles (92us)
      osc32k_arch_wrtlock: false
      osc8m_arch_calib: 0
-      osc8m_arch_enable: false
+      osc8m_arch_enable: true
      osc8m_arch_ondemand: true
      osc8m_arch_overwrite_calibration: false
      osc8m_arch_runstdby: false
@@ -539,7 +539,7 @@ drivers:
      xosc32k_arch_aampen: false
      xosc32k_arch_en1k: false
      xosc32k_arch_en32k: true
-      xosc32k_arch_enable: true
+      xosc32k_arch_enable: false
      xosc32k_arch_ondemand: false
      xosc32k_arch_runstdby: false
      xosc32k_arch_startup: 122 us

--- a/bootloader/atmel_start_prj/config/hpl_gclk_config.h
+++ b/bootloader/atmel_start_prj/config/hpl_gclk_config.h
@@ -76,7 +76,7 @@
 // <i>
 // <id> gclk_gen_0_div
 #ifndef CONF_GCLK_GEN_0_DIV
-#define CONF_GCLK_GEN_0_DIV 1
+#define CONF_GCLK_GEN_0_DIV 2
 #endif
 // </h>
@@ -142,7 +142,7 @@
 // <i> This defines the clock source for generic clock generator 1
 // <id> gclk_gen_1_oscillator
 #ifndef CONF_GCLK_GEN_1_SRC
-#define CONF_GCLK_GEN_1_SRC GCLK_GENCTRL_SRC_XOSC32K
+#define CONF_GCLK_GEN_1_SRC GCLK_GENCTRL_SRC_OSC8M
 #endif
 // </h>
@@ -151,7 +151,7 @@
 // <i>
 // <id> gclk_gen_1_div
 #ifndef CONF_GCLK_GEN_1_DIV
-#define CONF_GCLK_GEN_1_DIV 1
+#define CONF_GCLK_GEN_1_DIV 32
 #endif
 // </h>
@@ -159,7 +159,7 @@
 // <i> Indicates whether generic clock 2 configuration is enabled or not
 // <id> enable_gclk_gen_2
 #ifndef CONF_GCLK_GENERATOR_2_CONFIG
-#define CONF_GCLK_GENERATOR_2_CONFIG 1
+#define CONF_GCLK_GENERATOR_2_CONFIG 0
 #endif
 // <h> Generic Clock Generator Control
@@ -202,7 +202,7 @@
 // <i> Indicates whether Generic Clock Generator Enable is enabled or not
 // <id> gclk_arch_gen_2_enable
 #ifndef CONF_GCLK_GEN_2_GENEN
-#define CONF_GCLK_GEN_2_GENEN 1
+#define CONF_GCLK_GEN_2_GENEN 0
 #endif
 // <y> Generic clock generator 2 source

--- a/bootloader/atmel_start_prj/config/hpl_sysctrl_config.h
+++ b/bootloader/atmel_start_prj/config/hpl_sysctrl_config.h
@@ -46,7 +46,7 @@
 // <i> Indicates whether configuration for OSC8M is enabled or not
 // <id> enable_osc8m
 #ifndef CONF_OSC8M_CONFIG
-#define CONF_OSC8M_CONFIG 0
+#define CONF_OSC8M_CONFIG 1
 #endif
 // <h> 8MHz Internal Oscillator (OSC8M) Control
@@ -54,7 +54,7 @@
 // <i> Indicates whether Internal 8 Mhz Oscillator is enabled or not
 // <id> osc8m_arch_enable
 #ifndef CONF_OSC8M_ENABLE
-#define CONF_OSC8M_ENABLE 0
+#define CONF_OSC8M_ENABLE 1
 #endif
 // <q> On Demand Control
@@ -197,7 +197,7 @@
 // <i> Indicates whether configuration for External 32K Osc is enabled or not
 // <id> enable_xosc32k
 #ifndef CONF_XOSC32K_CONFIG
-#define CONF_XOSC32K_CONFIG 1
+#define CONF_XOSC32K_CONFIG 0
 #endif
 // <h> 32kHz External Crystal Oscillator (XOSC32K) Control
@@ -205,7 +205,7 @@
 // <i> Indicates whether External 32K Oscillator is enabled or not
 // <id> xosc32k_arch_enable
 #ifndef CONF_XOSC32K_ENABLE
-#define CONF_XOSC32K_ENABLE 1
+#define CONF_XOSC32K_ENABLE 0
 #endif
 // <q> On Demand

--- a/bootloader/atmel_start_prj/config/peripheral_clk_config.h
+++ b/bootloader/atmel_start_prj/config/peripheral_clk_config.h
@@ -9,7 +9,7 @@
 * \brief CPU's Clock frequency
 */
 #ifndef CONF_CPU_FREQUENCY
-#define CONF_CPU_FREQUENCY 48000000
+#define CONF_CPU_FREQUENCY 24000000
 #endif
 // <y> Core Clock Source
@@ -65,7 +65,7 @@
 * \brief SERCOM2's Core Clock frequency
 */
 #ifndef CONF_GCLK_SERCOM2_CORE_FREQUENCY
-#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 48000000
+#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 24000000
 #endif
 /**