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DIOT Monitoring Module
DIOT Monitoring Module
Commit c68eb331 authored by Adam Wujek's avatar Adam Wujek
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bootloader: clock changes 10 

Signed-off-by: 's avatarAdam Wujek <dev_public@wujek.eu>
parent 8f7f141c
Pipeline #3667 passed with stage
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    Showing with 6 additions and 6 deletions
    bootloader/atmel_start_prj/atmel_start_config.atstart
    View file @ c68eb331
    ......@@ -64,8 +64,8 @@ drivers:
    gclk_arch_gen_1_idc: false
    gclk_arch_gen_1_oe: false
    gclk_arch_gen_1_oov: false
    gclk_arch_gen_2_RUNSTDBY: false
    gclk_arch_gen_2_enable: false
    gclk_arch_gen_2_RUNSTDBY: true
    gclk_arch_gen_2_enable: true
    gclk_arch_gen_2_idc: false
    gclk_arch_gen_2_oe: false
    gclk_arch_gen_2_oov: false
    ......@@ -139,7 +139,7 @@ drivers:
    cpu_clock_source: Generic clock generator 0
    cpu_div: '1'
    enable_cpu_clock: true
    nvm_wait_states: '1'
    nvm_wait_states: '0'
    optional_signals: []
    variant: null
    clocks:
    ......
    bootloader/atmel_start_prj/config/hpl_gclk_config.h
    View file @ c68eb331
    ......@@ -167,7 +167,7 @@
    // <i> Indicates whether Run in Standby is enabled or not
    // <id> gclk_arch_gen_2_RUNSTDBY
    #ifndef CONF_GCLK_GEN_2_RUNSTDBY
    #define CONF_GCLK_GEN_2_RUNSTDBY 0
    #define CONF_GCLK_GEN_2_RUNSTDBY 1
    #endif
    // <q> Divide Selection
    ......@@ -202,7 +202,7 @@
    // <i> Indicates whether Generic Clock Generator Enable is enabled or not
    // <id> gclk_arch_gen_2_enable
    #ifndef CONF_GCLK_GEN_2_GENEN
    #define CONF_GCLK_GEN_2_GENEN 0
    #define CONF_GCLK_GEN_2_GENEN 1
    #endif
    // <y> Generic clock generator 2 source
    ......
    bootloader/atmel_start_prj/config/hpl_pm_config.h
    View file @ c68eb331
    ......@@ -59,7 +59,7 @@
    // <15=> 15
    // <id> nvm_wait_states
    #ifndef CONF_NVM_WAIT_STATE
    #define CONF_NVM_WAIT_STATE 1
    #define CONF_NVM_WAIT_STATE 0
    #endif
    // </h>
    ......
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