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DIOT Monitoring Module
DIOT Monitoring Module
Commit 9e119357 authored by Christos Gentsos's avatar Christos Gentsos
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Bootloader: update START, use internal 8MHz osc, set core to 24MHz

parent 1bbe930e
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Showing with 111 additions and 54 deletions
bootloader/atmel_start_prj/AtmelStart.env_conf
View file @ 9e119357
<environment>
<configurations/>
<device-packs>
<device-pack device="ATSAMD21G18A" name="SAMD21_DFP" vendor="Atmel" version="1.3.331"/>
<device-pack device="ATSAMD21G18A" name="SAMD21_DFP" vendor="Atmel" version="1.3.395"/>
</device-packs>
</environment>
bootloader/atmel_start_prj/atmel_start_config.atstart
View file @ 9e119357
......@@ -2,12 +2,17 @@ format_version: '2'
name: My Project
versions:
api: '1.0'
backend: 1.6.148
commit: 605f106ab95776472e3febf2fac2471441fb1816
content: 1.0.1600
content_pack_name: acme-packs-all
backend: 1.8.580
commit: f3d8d96e294de8dee688333bbbe8d8458a4f6b4c
content: unknown
content_pack_name: unknown
format: '2'
frontend: 1.6.1881
frontend: 1.8.580
packs_version_avr8: 1.0.1463
packs_version_qtouch: unknown
packs_version_sam: 1.0.1726
version_backend: 1.8.580
version_frontend: ''
board:
identifier: CustomBoard
device: SAMD21G18A-MF
......@@ -21,14 +26,34 @@ drivers:
functionality: System
api: HAL:HPL:GCLK
configuration:
$input: 48000000
$input_id: Digital Frequency Locked Loop (DFLL48M)
RESERVED_InputFreq: 48000000
RESERVED_InputFreq_id: Digital Frequency Locked Loop (DFLL48M)
_$freq_output_Generic clock generator 0: 24000000
_$freq_output_Generic clock generator 1: 31250
_$freq_output_Generic clock generator 2: 48000000
_$freq_output_Generic clock generator 3: 400000
_$freq_output_Generic clock generator 4: 400000
_$freq_output_Generic clock generator 5: 400000
_$freq_output_Generic clock generator 6: 400000
_$freq_output_Generic clock generator 7: 400000
enable_gclk_gen_0: true
enable_gclk_gen_0__externalclock: 1000000
enable_gclk_gen_1: true
enable_gclk_gen_2: true
enable_gclk_gen_1__externalclock: 1000000
enable_gclk_gen_2: false
enable_gclk_gen_2__externalclock: 1000000
enable_gclk_gen_3: true
enable_gclk_gen_3__externalclock: 1000000
enable_gclk_gen_4: false
enable_gclk_gen_4__externalclock: 1000000
enable_gclk_gen_5: false
enable_gclk_gen_5__externalclock: 1000000
enable_gclk_gen_6: false
enable_gclk_gen_6__externalclock: 1000000
enable_gclk_gen_7: false
enable_gclk_gen_7__externalclock: 1000000
gclk_arch_gen_0_RUNSTDBY: false
gclk_arch_gen_0_enable: true
gclk_arch_gen_0_idc: false
......@@ -40,7 +65,7 @@ drivers:
gclk_arch_gen_1_oe: false
gclk_arch_gen_1_oov: false
gclk_arch_gen_2_RUNSTDBY: false
gclk_arch_gen_2_enable: true
gclk_arch_gen_2_enable: false
gclk_arch_gen_2_idc: false
gclk_arch_gen_2_oe: false
gclk_arch_gen_2_oov: false
......@@ -69,12 +94,12 @@ drivers:
gclk_arch_gen_7_idc: false
gclk_arch_gen_7_oe: false
gclk_arch_gen_7_oov: false
gclk_gen_0_div: 1
gclk_gen_0_div: 2
gclk_gen_0_div_sel: false
gclk_gen_0_oscillator: Digital Frequency Locked Loop (DFLL48M)
gclk_gen_1_div: 1
gclk_gen_1_div: 32
gclk_gen_1_div_sel: false
gclk_gen_1_oscillator: 32kHz External Crystal Oscillator (XOSC32K)
gclk_gen_1_oscillator: 8MHz Internal Oscillator (OSC8M)
gclk_gen_2_div: 1
gclk_gen_2_div_sel: false
gclk_gen_2_oscillator: Digital Frequency Locked Loop (DFLL48M)
......@@ -103,6 +128,11 @@ drivers:
functionality: System
api: HAL:HPL:PM
configuration:
$input: 24000000
$input_id: Generic clock generator 0
RESERVED_InputFreq: 24000000
RESERVED_InputFreq_id: Generic clock generator 0
_$freq_output_CPU: 24000000
apba_div: '1'
apbb_div: '1'
apbc_div: '1'
......@@ -447,6 +477,14 @@ drivers:
functionality: System
api: HAL:HPL:SYSCTRL
configuration:
$input: 31250
$input_id: Generic clock generator 1
RESERVED_InputFreq: 31250
RESERVED_InputFreq_id: Generic clock generator 1
_$freq_output_8MHz Internal Oscillator (OSC8M): 1000000
_$freq_output_Digital Frequency Locked Loop (DFLL48M): 48000000
_$freq_output_External Crystal Oscillator 0.4-32MHz (XOSC): 400000
_$freq_output_Fractional Digital Phase Locked Loop (FDPLL96M): 45775390.625
dfll48m_arch_bplckc: false
dfll48m_arch_calibration: false
dfll48m_arch_ccdis: true
......@@ -468,10 +506,10 @@ drivers:
enable_dfll48m: true
enable_fdpll96m: false
enable_osc32k: false
enable_osc8m: false
enable_osc8m: true
enable_osculp32k: false
enable_xosc: false
enable_xosc32k: true
enable_xosc32k: false
fdpll96m_arch_enable: false
fdpll96m_arch_lbypass: true
fdpll96m_arch_ondemand: false
......@@ -490,7 +528,7 @@ drivers:
osc32k_arch_startup: 3 Clock Cycles (92us)
osc32k_arch_wrtlock: false
osc8m_arch_calib: 0
osc8m_arch_enable: false
osc8m_arch_enable: true
osc8m_arch_ondemand: true
osc8m_arch_overwrite_calibration: false
osc8m_arch_runstdby: false
......@@ -501,7 +539,7 @@ drivers:
xosc32k_arch_aampen: false
xosc32k_arch_en1k: false
xosc32k_arch_en32k: true
xosc32k_arch_enable: true
xosc32k_arch_enable: false
xosc32k_arch_ondemand: false
xosc32k_arch_runstdby: false
xosc32k_arch_startup: 122 us
......@@ -551,3 +589,4 @@ pads:
user_label: ADDR0
configuration: null
toolchain_options: []
static_files: []
bootloader/atmel_start_prj/config/hpl_gclk_config.h
View file @ 9e119357
......@@ -76,7 +76,7 @@
// <i>
// <id> gclk_gen_0_div
#ifndef CONF_GCLK_GEN_0_DIV
#define CONF_GCLK_GEN_0_DIV 1
#define CONF_GCLK_GEN_0_DIV 2
#endif
// </h>
......@@ -142,7 +142,7 @@
// <i> This defines the clock source for generic clock generator 1
// <id> gclk_gen_1_oscillator
#ifndef CONF_GCLK_GEN_1_SRC
#define CONF_GCLK_GEN_1_SRC GCLK_GENCTRL_SRC_XOSC
#define CONF_GCLK_GEN_1_SRC GCLK_GENCTRL_SRC_OSC8M
#endif
// </h>
......@@ -151,7 +151,7 @@
// <i>
// <id> gclk_gen_1_div
#ifndef CONF_GCLK_GEN_1_DIV
#define CONF_GCLK_GEN_1_DIV 256
#define CONF_GCLK_GEN_1_DIV 32
#endif
// </h>
......@@ -159,7 +159,7 @@
// <i> Indicates whether generic clock 2 configuration is enabled or not
// <id> enable_gclk_gen_2
#ifndef CONF_GCLK_GENERATOR_2_CONFIG
#define CONF_GCLK_GENERATOR_2_CONFIG 1
#define CONF_GCLK_GENERATOR_2_CONFIG 0
#endif
// <h> Generic Clock Generator Control
......@@ -202,7 +202,7 @@
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
// <id> gclk_arch_gen_2_enable
#ifndef CONF_GCLK_GEN_2_GENEN
#define CONF_GCLK_GEN_2_GENEN 1
#define CONF_GCLK_GEN_2_GENEN 0
#endif
// <y> Generic clock generator 2 source
......
bootloader/atmel_start_prj/config/hpl_sysctrl_config.h
View file @ 9e119357
......@@ -46,7 +46,7 @@
// <i> Indicates whether configuration for OSC8M is enabled or not
// <id> enable_osc8m
#ifndef CONF_OSC8M_CONFIG
#define CONF_OSC8M_CONFIG 0
#define CONF_OSC8M_CONFIG 1
#endif
// <h> 8MHz Internal Oscillator (OSC8M) Control
......@@ -54,7 +54,7 @@
// <i> Indicates whether Internal 8 Mhz Oscillator is enabled or not
// <id> osc8m_arch_enable
#ifndef CONF_OSC8M_ENABLE
#define CONF_OSC8M_ENABLE 0
#define CONF_OSC8M_ENABLE 1
#endif
// <q> On Demand Control
......@@ -197,7 +197,7 @@
// <i> Indicates whether configuration for External 32K Osc is enabled or not
// <id> enable_xosc32k
#ifndef CONF_XOSC32K_CONFIG
#define CONF_XOSC32K_CONFIG 1
#define CONF_XOSC32K_CONFIG 0
#endif
// <h> 32kHz External Crystal Oscillator (XOSC32K) Control
......@@ -205,7 +205,7 @@
// <i> Indicates whether External 32K Oscillator is enabled or not
// <id> xosc32k_arch_enable
#ifndef CONF_XOSC32K_ENABLE
#define CONF_XOSC32K_ENABLE 1
#define CONF_XOSC32K_ENABLE 0
#endif
// <q> On Demand
......
bootloader/atmel_start_prj/config/peripheral_clk_config.h
View file @ 9e119357
......@@ -9,7 +9,7 @@
* \brief CPU's Clock frequency
*/
#ifndef CONF_CPU_FREQUENCY
#define CONF_CPU_FREQUENCY 48000000
#define CONF_CPU_FREQUENCY 24000000
#endif
// <y> Core Clock Source
......@@ -65,7 +65,7 @@
* \brief SERCOM2's Core Clock frequency
*/
#ifndef CONF_GCLK_SERCOM2_CORE_FREQUENCY
#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 48000000
#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 24000000
#endif
/**
......
bootloader/atmel_start_prj/hpl/dmac/hpl_dmac.c
View file @ 9e119357
......@@ -216,7 +216,6 @@ static inline void _dmac_handler(void)
hri_dmac_write_CHID_reg(DMAC, channel);
flag_status = hri_dmac_get_CHINTFLAG_reg(DMAC, DMAC_CHINTFLAG_MASK);
hri_dmac_write_CHID_reg(DMAC, current_channel);
if (flag_status & DMAC_CHINTFLAG_TERR) {
hri_dmac_clear_CHINTFLAG_TERR_bit(DMAC);
......@@ -225,6 +224,7 @@ static inline void _dmac_handler(void)
hri_dmac_clear_CHINTFLAG_TCMPL_bit(DMAC);
tmp_resource->dma_cb.transfer_done(tmp_resource);
}
hri_dmac_write_CHID_reg(DMAC, current_channel);
}
/**
......
bootloader/atmel_start_prj/hpl/sercom/hpl_sercom.c
View file @ 9e119357
......@@ -1672,6 +1672,12 @@ static struct i2cs_configuration _i2css[] = {
#if CONF_SERCOM_5_I2CS_ENABLE == 1
I2CS_CONFIGURATION(5),
#endif
#if CONF_SERCOM_6_I2CS_ENABLE == 1
I2CS_CONFIGURATION(6),
#endif
#if CONF_SERCOM_7_I2CS_ENABLE == 1
I2CS_CONFIGURATION(7),
#endif
};
#endif
......@@ -1713,6 +1719,10 @@ int32_t _i2c_s_async_init(struct _i2c_s_async_device *const device, void *const
NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(hw));
NVIC_EnableIRQ((IRQn_Type)_sercom_get_irq_num(hw));
// Enable Address Match and PREC interrupt by default.
hri_sercomi2cs_set_INTEN_AMATCH_bit(hw);
hri_sercomi2cs_set_INTEN_PREC_bit(hw);
return ERR_NONE;
}
......@@ -1910,12 +1920,19 @@ int32_t _i2c_s_async_set_irq_state(struct _i2c_s_async_device *const device, con
static void _sercom_i2c_s_irq_handler(struct _i2c_s_async_device *device)
{
void * hw = device->hw;
uint32_t flags = hri_sercomi2cm_read_INTFLAG_reg(hw);
uint32_t flags = hri_sercomi2cs_read_INTFLAG_reg(hw);
if (flags & SERCOM_I2CS_INTFLAG_ERROR) {
ASSERT(device->cb.error);
device->cb.error(device);
} else if (flags & SERCOM_I2CS_INTFLAG_DRDY) {
}
if (flags & SERCOM_I2CS_INTFLAG_AMATCH) {
hri_sercomi2cs_clear_INTFLAG_AMATCH_bit(hw);
}
if (flags & SERCOM_I2CS_INTFLAG_PREC) {
hri_sercomi2cs_clear_INTFLAG_PREC_bit(hw);
}
if (flags & SERCOM_I2CS_INTFLAG_DRDY) {
if (!hri_sercomi2cs_get_STATUS_DIR_bit(hw)) {
ASSERT(device->cb.rx_done);
device->cb.rx_done(device, hri_sercomi2cs_read_DATA_reg(hw));
......@@ -1923,6 +1940,7 @@ static void _sercom_i2c_s_irq_handler(struct _i2c_s_async_device *device)
ASSERT(device->cb.tx);
device->cb.tx(device);
}
hri_sercomi2cs_clear_INTFLAG_DRDY_bit(hw);
#if (CONF_MCLK_LPDIV) != (CONF_MCLK_CPUDIV)
/* Adding grace time while waiting for SCL line to be released */
hri_sercomi2cs_clear_STATUS_reg(hw, 0);
......
bootloader/atmel_start_prj/samd21a/include/component-version.h
View file @ 9e119357
......@@ -3,7 +3,7 @@
*
* \brief Component version header file
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
* Copyright (c) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
......@@ -43,7 +43,7 @@
// The build number does not refer to the component, but to the build number
// of the device pack that provides the component.
//
#define BUILD_NUMBER 331
#define BUILD_NUMBER 395
//
// The COMPONENT_VERSION_STRING is a string (enclosed in ") that can be used for logging or embedding.
......@@ -58,7 +58,7 @@
// "%Y-%m-%d %H:%M:%S"
//
//
#define COMPONENT_DATE_STRING "2018-08-17 08:46:55"
#define COMPONENT_DATE_STRING "2019-09-19 13:04:38"
#endif/* #ifndef _COMPONENT_VERSION_H_INCLUDED */
bootloader/atmel_start_prj/samd21a/include/sam.h
View file @ 9e119357
......@@ -3,7 +3,7 @@
*
* \brief Top level header file
*
* Copyright (c) 2018 Microchip Technology Inc.
* Copyright (c) 2019 Microchip Technology Inc.
*
* \license_start
*
......@@ -30,34 +30,34 @@
#ifndef _SAM_
#define _SAM_
#if defined(__SAMD21E15A__) || defined(__ATSAMD21E15A__)
#include "samd21e15a.h"
#elif defined(__SAMD21E16A__) || defined(__ATSAMD21E16A__)
#if defined(__SAMD21E16A__) || defined(__ATSAMD21E16A__)
#include "samd21e16a.h"
#elif defined(__SAMD21E17A__) || defined(__ATSAMD21E17A__)
#include "samd21e17a.h"
#elif defined(__SAMD21E18A__) || defined(__ATSAMD21E18A__)
#include "samd21e18a.h"
#elif defined(__SAMD21G15A__) || defined(__ATSAMD21G15A__)
#include "samd21g15a.h"
#elif defined(__SAMD21G16A__) || defined(__ATSAMD21G16A__)
#include "samd21g16a.h"
#elif defined(__SAMD21J16A__) || defined(__ATSAMD21J16A__)
#include "samd21j16a.h"
#elif defined(__SAMD21E15A__) || defined(__ATSAMD21E15A__)
#include "samd21e15a.h"
#elif defined(__SAMD21J18A__) || defined(__ATSAMD21J18A__)
#include "samd21j18a.h"
#elif defined(__SAMD21G17A__) || defined(__ATSAMD21G17A__)
#include "samd21g17a.h"
#elif defined(__SAMD21G17AU__) || defined(__ATSAMD21G17AU__)
#include "samd21g17au.h"
#elif defined(__SAMD21G18A__) || defined(__ATSAMD21G18A__)
#include "samd21g18a.h"
#elif defined(__SAMD21G18AU__) || defined(__ATSAMD21G18AU__)
#include "samd21g18au.h"
#elif defined(__SAMD21J15A__) || defined(__ATSAMD21J15A__)
#include "samd21j15a.h"
#elif defined(__SAMD21J16A__) || defined(__ATSAMD21J16A__)
#include "samd21j16a.h"
#elif defined(__SAMD21G16A__) || defined(__ATSAMD21G16A__)
#include "samd21g16a.h"
#elif defined(__SAMD21G15A__) || defined(__ATSAMD21G15A__)
#include "samd21g15a.h"
#elif defined(__SAMD21J17A__) || defined(__ATSAMD21J17A__)
#include "samd21j17a.h"
#elif defined(__SAMD21J18A__) || defined(__ATSAMD21J18A__)
#include "samd21j18a.h"
#elif defined(__SAMD21G17AU__) || defined(__ATSAMD21G17AU__)
#include "samd21g17au.h"
#elif defined(__SAMD21E17A__) || defined(__ATSAMD21E17A__)
#include "samd21e17a.h"
#elif defined(__SAMD21G18AU__) || defined(__ATSAMD21G18AU__)
#include "samd21g18au.h"
#elif defined(__SAMD21E18A__) || defined(__ATSAMD21E18A__)
#include "samd21e18a.h"
#elif defined(__SAMD21G18A__) || defined(__ATSAMD21G18A__)
#include "samd21g18a.h"
#else
#error Library does not support the specified device
#endif
......
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